User manual TEXAS INSTRUMENTS TUSB1210 DATA MANUAL REV A

[. . . ] TUSB1210 Standalone USB Transceiver Chip Silicon Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLLSE09A November 2009 ­ Revised July 2010 TUSB1210 SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 www. ti. com Contents 1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Terminal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] A disconnect on the far end of the cable causes the impedance seen by the transmitter to double thereby doubling the differential amplitude seen on the DP/DM lines. HS Transmitter PARAMETER VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK THSR THSR ZHSDRV High-speed idle level High-speed data signaling high High-speed data signaling low Chirp J level (differential voltage) Chirp K level (differential voltage) Rise Time (10% - 90%) Fall time (10% - 90%) Driver output resistance (which also serves as high-speed termination) Ref. USB2. 0, covered by eye diagram COMMENTS MIN -10 360 -10 700 -900 500 500 40. 5 479. 76 49. 5 480. 24 TYP MAX 10 440 10 1100 -500 UNIT mV mV mV mV mV ps ps Mb/s THSDRAT High-speed data range Data source jitter Downstream eye diagram Upstream eye diagram 22 USB Connectivity Submit Documentation Feedback Product Folder Link(s): TUSB1210 Copyright © 2009­2010, Texas Instruments Incorporated TUSB1210 www. ti. com SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 6. 3. 3. 6 UART Transceiver In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a direct access to the FS/LS analog transmitter and receiver. USB UART Interface Timing Parameters PARAMETER tPH_DP_CON tPH_DISC_DET fUART_DFLT Phone D+ connect time Phone D+ disconnect time Default UART signaling rate (typical rate) MIN 100 150 9600 MAX UNIT ms ms bps Figure 6-1. CEA-2011/UART Transceiver PARAMETER UART Transmitter CEA-2011 tPH_UART_EDGE VOH_SER VOL_SER VIH_SER VIL_SER VTH Phone UART edge rates Serial interface output high Serial interface output low UART Receiver CEA-2011 Serial interface input high Serial interface input low Switching threshold DP_PULLDOWN asserted DP_PULLDOWN asserted 0. 8 2 0. 8 2 V V V DP_PULLDOWN asserted ISOURCE = 4 mA ISINK = ­4 mA 2. 4 0 3. 3 0. 1 1 3. 6 0. 4 s V V COMMENTS MIN TYP MAX UNIT Copyright © 2009­2010, Texas Instruments Incorporated USB Connectivity Submit Documentation Feedback Product Folder Link(s): TUSB1210 23 TUSB1210 SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 www. ti. com Table 6-14. Pullup/Pulldown Resistors PARAMETER RPUI RPUA VIHZ VPH_DP_UP RPH_DP_DWN RPH_DM_DWN VIHZ High (floating) D+/­ Data line CINUB VOTG_DATA_LK G ZINP Upstream facing port On-the-go device leakage Input impedance exclusive of pullup/pulldown [1. 0] [2] Driver's outputs unloaded 300 22 75 0. 342 pF V k Pullups / pulldowns on both DP and DM lines 2. 7 3. 6 V Bus pullup resistor on upstream port (idle bus) Bus pullup resistor on upstream port (receiving) High (floating) Phone D+ pullup voltage Pulldown Resistors Phone D+/­ pulldown Driver's outputs unloaded 14. 25 18 24. 8 k Bus idle Bus driven / driver's outputs unloaded Pullups / pulldowns on both DP and DM lines Driver's outputs unloaded COMMENTS MIN 0. 9 1. 425 2. 7 3 3. 3 TYP 1. 1 2. 2 MAX 1. 575 3. 09 3. 6 3. 6 V V UNIT k 6. 3. 4 OTG Electrical Characteristics The on-the-go (OTG) block integrates three main functions: · The USB plug detection function on VBUS and ID · The ID resistor detection · The VBUS level detection Table 6-15. OTG VBUS Electrical PARAMETER COMMENTS MIN 0. 8 4. 4 0. 2 2. 1 SRP (VBUS pulsing) capable A-device not driving VBUS 5. 25 V / 8 mA, Pullup voltage = 3 V (5. 25 V ­ 3 V) / 8 mA, Pullup voltage = 3 V 0 to 2. 1 V with < 13 mF load 0. 8 to 2. 0 V with > 97 mF load TBD 40 0. 656 0. 281 TYP 1. 1 4. 5 0. 5 2. 4 70 10 1 2 TBD MAX 1. 4 4. 625 0. 8 2. 7 100 UNIT V V V V k k k ms ms VBUS Comparators VA_SESS_VLD VA_VBUS_VLD VB_SESS_END VB_SESS_VLD VBUS Line RA_BUS_IN RB_SRP_DWN RB_SRP_UP tRISE_SRP_UP_MAX tRISE_SRP_UP_MIN A-device VBUS input impedance to ground B-device VBUS SRP pulldown B-device VBUS SRP pullup B-device VBUS SRP rise time maximum for OTG-A communication B-device VBUS SRP rise time minimum for standard host connection A-device session valid A-device VBUS valid B-device session end B-device session valid 24 USB Connectivity Submit Documentation Feedback Product Folder Link(s): TUSB1210 Copyright © 2009­2010, Texas Instruments Incorporated TUSB1210 www. ti. com SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 Table 6-16. OTG ID Electrical PARAMETER ID Comparators -- ID External Resistors Specifications RID_GND RID_FLOAT RPH_ID_UP VPH_ID_UP ID ground comparator ID Float comparator ID Line Phone ID pullup to VPH_ID_UP Phone ID pullup voltage ID line maximum voltage ID unloaded (VRUSB) Connected to VRUSB 70 2. 5 90 286 3. 2 5. 25 k V V ID_GND interrupt ID_FLOAT interrupt 4 200 20 35 500 k k COMMENTS MIN TYP MAX UNIT Copyright © 2009­2010, Texas Instruments Incorporated USB Connectivity Submit Documentation Feedback Product Folder Link(s): TUSB1210 25 TUSB1210 SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 www. ti. com 7 External Components Table 7-1. TUSB1210 External Components FUNCTION VDDIO VDD33 VDD15 VDD18 COMPONENT Capacitor Capacitor Capacitor Capacitor Capacitor VBAT VBUS Capacitor Capacitor REFERENCE CVDDIO CVDD33 CVDD15 Int 1. 8V LDO CVDD18 Ext 1. 8V supply CVDD18 CBYP CVBUS 2. 2 mF See table 1. 2 100 nF VALUE 100 nF 2. 2 mF 2. 2 mF 2. 2 mF NOTE Suggested value, application dependent Range: [0. 45 mF : 6. 5 mF] , ESR = [0 : 600 m] for f> 10 kHz Range: [0. 45 mF : 6. 5 mF] , ESR = [0 : 600 m] for f> 10 kHz Range: [0. 45 mF : 6. 5 mF] , ESR = [0 : 600 m] for f> 10 kHz Suggested value, application dependent Range: [0. 45 mF : 6. 5 mF] , ESR = [0 : 600 m] for f> 10 kHz Place close to USB connector LINK Figure 9-1 Figure 9-1 Figure 9-1 Figure 9-1 Figure 9-1 Figure 9-1 Figure 9-1 Table 7-2. TUSB1210 VBUS Capacitors FUNCTION VBUS - HOST VBUS ­ DEVICE VBUS - OTG COMPONENT Capacitor Capacitor Capacitor REFERENCE CVBUS CVBUS CVBUS VALUE >120 mF 4. 7 mF 4. 7 mF Range: 1. 0 mF to 10. 0 mF Range: 1. 0 mF to 6. 5 mF NOTE LINK Figure 9-1 Figure 9-1 Figure 9-1 26 External Components Submit Documentation Feedback Product Folder Link(s): TUSB1210 Copyright © 2009­2010, Texas Instruments Incorporated TUSB1210 www. ti. com SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 8 8. 1 Register Map TUSB1210 Product Table 8-1. USB Register Summary REGISTER NAME VENDOR_ID_LO VENDOR_ID_HI PRODUCT_ID_LO PRODUCT_ID_HI FUNC_CTRL FUNC_CTRL_SET FUNC_CTRL_CLR IFC_CTRL IFC_CTRL_SET IFC_CTRL_CLR OTG_CTRL OTG_CTRL_SET OTG_CTRL_CLR USB_INT_EN_RISE USB_INT_EN_RISE_SET USB_INT_EN_RISE_CLR USB_INT_EN_FALL USB_INT_EN_FALL_SET USB_INT_EN_FALL_CLR USB_INT_STS USB_INT_LATCH DEBUG SCRATCH_REG SCRATCH_REG_SET SCRATCH_REG_CLR Reserved ACCESS_EXT_REG_SET Reserved VENDOR_SPECIFIC1 VENDOR_SPECIFIC1_SET VENDOR_SPECIFIC1_CLR VENDOR_SPECIFIC2 VENDOR_SPECIFIC2_SET VENDOR_SPECIFIC2_CLR VENDOR_SPECIFIC1_STS VENDOR_SPECIFIC1_LATCH VENDOR_SPECIFIC3 VENDOR_SPECIFIC3_SET VENDOR_SPECIFIC3_CLR TYPE R R R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R RW RW RW R RW R RW RW RW RW RW RW R R RW RW RW REGISTER WIDTH (BITS) 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PHYSICAL ADDRESS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x2E 0x2F 0x30 0x3C 0x3D 0x3E 0x3F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 Copyright © 2009­2010, Texas Instruments Incorporated Register Map Submit Documentation Feedback Product Folder Link(s): TUSB1210 27 TUSB1210 SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 www. ti. com 8. 1. 1 VENDOR_ID_LO ADDRESS OFFSET PHYSICAL ADDRESS DESCRIPTION TYPE WRITE LATENCY 7 6 5 4 3 2 1 0 0x00 0x00 R INSTANCE USB_SCUSB Lower byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451) VENDOR_ID BITS 7:00 FIELD NAME VENDOR_ID DESCRIPTION TYPE R RESET 0x51 8. 1. 2 VENDOR_ID_HI ADDRESS OFFSET PHYSICAL ADDRESS DESCRIPTION TYPE WRITE LATENCY 7 6 5 4 3 2 1 0 0x01 0x01 R INSTANCE USB_SCUSB Upper byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451) VENDOR_ID BITS 7:00 FIELD NAME VEN DOR_ID DESCRIPTION TYPE R RESET 0x04 8. 1. 3 PRODUCT_ID_LO ADDRESS OFFSET PHYSICAL ADDRESS DESCRIPTION TYPE WRITE LATENCY 7 6 5 4 3 2 1 0 0x02 0x02 INSTANCE USB_SCUSB Lower byte of Product ID supplied by Vendor (TUSB1210 Product ID is 0x1507). R PRODUCT_ID BITS 7:00 FIELD NAME DESCRIPTION TYPE R RESET 0x07 PRODUCT_ID 28 Register Map Submit Documentation Feedback Product Folder Link(s): TUSB1210 Copyright © 2009­2010, Texas Instruments Incorporated TUSB1210 www. ti. com SLLSE09A ­ NOVEMBER 2009 ­ REVISED JULY 2010 8. 1. 4 PRODUCT_ID_HI ADDRESS OFFSET PHYSICAL ADDRESS DESCRIPTION TYPE WRITE LATENCY 7 6 5 4 3 2 1 0 0x03 0x03 INSTANCE USB_SCUSB Upper byte of Product ID supplied by Vendor (TUSB1210 Product ID is 0x1507). R PRODUCT_ID BITS 7:00 FIELD NAME DESCRIPTION TYPE R RESET 0x15 PRODUCT_ID 8. 1. 5 FUNC_CTRL ADDRESS OFFSET PHYSICAL ADDRESS DESCRIPTION TYPE WRITE LATENCY 7 Reserved 6 SUSPENDM 5 4 OPMODE 3 2 TERMSELECT 1 XCVRSELECT 0 0x04 0x04 INSTAN CE USB_SCUSB Controls UTMI function settings of the PHY. RW BITS 7 6 FIELD NAME Reserved SUSPENDM RESET DESCRIPTION Active low PHY suspend. In Low Power Mode the PHY power down all blocks except the full speed receiver, OTG comparators, and the ULPI interface pins. The PHY automatically set this bit to '1' when Low Power Mode is exited. Does not reset the ULPI interface or ULPI register set. Once set, the PHY asserts the DIR signal and reset the UTMI core. When the reset is completed, the PHY de-asserts DIR and clears this bit. After de-asserting DIR, the PHY re-assert DIR and send an RX command update. Note: This bit is auto-cleared, this explain why it can't be read at '1'. TYPE R RW RESET 0 1 5 RESET RW 0 4:03 OPMODE Select the required bit encoding style during transmit 0x0: 0x1: 0x2: 0x3: Normal operation Non-driving Disable bit-stuff and NRZI encoding Reserved (No SYNC and EOP generation feature not supported) RW 0x0 2 TERMSELECT Controls the internal 1. 5Kohms pull-up resistor and 45ohms HS terminations. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]