User manual TEXAS INSTRUMENTS TVP5157 DATA MANUAL 10-2010

[. . . ] TVP5158, TVP5157, TVP5156 Four-Channel NTSC/PAL Video Decoders With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for Security and Other Multi-Channel Video Applications Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES243D July 2009 ­ Revised October 2010 TVP5158, TVP5157, TVP5156 SLES243D ­ JULY 2009 ­ REVISED OCTOBER 2010 www. ti. com Contents 1 2 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] TVP5158 also supports audio cascade connection up to four devices cascade connected for 16-Ch audio input. 3. 9. 1 · · · · · · Features Four mono analog audio input channels ­ Requires external passive attenuator to support 2. 828-Vpp analog audio input Programmable Gain Amplifier (PGA) ­ Gain range: -12 ~ 0 dB, Gain Step: 1. 5 dB Integrated Anti-Aliasing Filter (AAF) 10-Bit Analog-to-Digital Converter Integrates Audio High-pass filter to eliminate low frequency hum Digital serial audio interface ­ 16-Bit Linear PCM, 8-Bit A-Law and 8-Bit µ-Law Data ­ I2S or DSP Format ­ Master and Slave mode operation ­ Up to 16 slots TDM output ­ 64 fs or 256 fs system clock Sampling Rate : 16 kHz, 8 kHz Audio Cascade connection ­ Up to 4 cascaded devices ­ I2S format ­ 256 fs system clock Audio Mixing Output ­ Audio ADC has one register to set mix ratio ­ The Mixing output pin SD_M can also be used for recording. Combined with the recording output pin SD_R, two I2S bit-streams can be output simultaneously. · · · 32 Functional Description Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5157 TVP5156 TVP5158, TVP5157, TVP5156 www. ti. com SLES243D ­ JULY 2009 ­ REVISED OCTOBER 2010 3. 9. 2 Audio Sub-System Functional Diagram Figure 3-17. Audio Sub-System Functional Diagram 3. 9. 3 Serial Audio Interface The timing for the TVP5158 serial audio interface is shown in Figure 3-18. The TVP5158 audio data output (SD_R) and frame sync pulse (LRCLK) are aligned with the falling edge of the bit clock (BCLK). The TVP5158 audio data is delayed one BCLK cycles from the falling edge of the frame sync pulse. In the DSP mode, the TVP5158 frame sync pulse is high for only one BCLK cycle. Copyright © 2009­2010, Texas Instruments Incorporated Functional Description 33 Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5157 TVP5156 TVP5158, TVP5157, TVP5156 SLES243D ­ JULY 2009 ­ REVISED OCTOBER 2010 www. ti. com 1/fs LRCLK_R BCLK_R SD_R LSB MSB LSB MSB LSB Data 1 (a) I S Format 1/fs LRCLK_R BCLK_R SD_R LSB MSB LSB MSB 2 Data 2 LSB Data 1 (b) DSP Format Data 2 Figure 3-18. Serial Audio Interface Timing Diagram 3. 9. 4 Analog Audio Input Clamping An internal clamping circuit provides mid-level clamping of all four analog audio inputs to a dc level of approximately 0. 625 V. 34 Functional Description Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5157 TVP5156 TVP5158, TVP5157, TVP5156 www. ti. com SLES243D ­ JULY 2009 ­ REVISED OCTOBER 2010 3. 9. 5 Audio Cascade Connection A IN_1 A IN_2 A IN_3 A IN_4 XTAL_IN X TAL XTAL_OUT OS C_OUT S D_CO BCLK_R LRCLK_R SD_R TVP5158 First Stage B CLK_CI SD_CI LRC LK_CI Record Output (A IN_1-AN_16) Mix Output SD_M A IN_5 A IN_6 A IN_7 A IN_8 S D_CO BC LK_R LRCLK_R SD_R BCLK_R LRCLK_R SD_R SD_M Record Output (A IN_5-AN_16) TVP5158 Second Stage XTAL_IN OS C_OUT SD_CI SD_M B CLK_CI LRC LK_CI A IN_9 AIN_10 AIN_11 AIN_12 S D_CO BC LK_R LRCLK_R SD_R BCLK_R LRCLK_R SD_R SD_M Record Output (A IN_9-AN_16) TVP5158 Third Stage XTAL_IN OS C_OUT SD_CI SD_M BC LK_CI LRCLK_CI AIN_13 AIN_14 AIN_15 AIN_16 S D_CO BC LK_R LRCLK_R SD _R BCLK_R LRCLK_R SD_R SD_M Record Output (A IN_13-AN_16) TVP5158 Last Stage XTAL_IN OS C_OUT SD_CI SD _M Figure 3-19. Audio Cascade Connection TVP5158 supports up to four devices cascaded together for audio cascade connection. The I2S output of master TVP5158 (1st stage) combines all audio channel data from cascaded TVP5158 devices. Key Features of Audio Cascade Connection · 16-Bit linear PCM data · I2S format · Bit Clock: 256 fs · All cascade inputs are always in slave mode · Second to fourth stage serial audio outputs are always in master mode · First stage serial audio output can be in either master or slave mode · Common clock source for all cascaded devices is required The Serial Audio Output Channel Assignment shown on Table 3-15. Copyright © 2009­2010, Texas Instruments Incorporated Functional Description 35 Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5157 TVP5156 TVP5158, TVP5157, TVP5156 SLES243D ­ JULY 2009 ­ REVISED OCTOBER 2010 www. ti. com Table 3-15. Serial Audio Output Channel Assignment I2S LRCLK_R Left tdm_ch tdm_out_pin SD_R 0 SD_M 0 (2 channel) SD_R 1 SD_M SD_R 0 SD_M 1 (4 channel) SD_R 1 SD_M SD_R 0 SD_M 2 (8 channel) SD_R 1 SD_M SD_R 0 SD_M 3 (12 channel) SD_R 1 SD_M SD_R 0 SD_M 4 (16 channel) SD_R 1 SD_M DSP Format tdm_ch tdm_out_pin SD_R 0 SD_M 0 (2 channel) SD_R 1 SD_M SD_R 0 SD_M 1 (4 channel) SD_R 1 SD_M SD_R 0 SD_M 2 (8 channel) SD_R 1 SD_M SD_R 0 SD_M 3 (12 channel) SD_R 1 SD_M SD_R 0 SD_M 4 (16 channel) SD_R 1 SD_M AIN_3 AIN_7 AIN_11 AIN_15 AIN_4 AIN_8 AIN_12 AIN_16 AIN_1 AIN_5 AIN_9 AIN_13 AIN_2 AIN_6 AIN_10 AIN_14 AIN_3 AIN_1 AIN_7 AIN_3 AIN_11 AIN_5 AIN_4 AIN_7 AIN_8 AIN_9 AIN_12 AIN_11 AIN_13 AIN_15 AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12 AIN_14 AIN_16 AIN_1 AIN_5 AIN_9 AIN_2 AIN_6 AIN_10 AIN_3 AIN_1 AIN_7 AIN_3 AIN_4 AIN_5 AIN_8 AIN_7 AIN_9 AIN_11 AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12 AIN_1 AIN_5 AIN_2 AIN_6 AIN_3 AIN_1 AIN_4 AIN_3 AIN_5 AIN_7 AIN_2 AIN_4 AIN_6 AIN_8 AIN_1 AIN_2 AIN_2 AIN_1 AIN_3 AIN_2 AIN_4 AIN_1 Slot 1 AIN_1 Slot 2 AIN_2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Slot 16 AIN_3 AIN_7 AIN_11 AIN_15 AIN_4 AIN_8 AIN_12 AIN_16 AIN_1 AIN_5 AIN_9 AIN_13 AIN_2 AIN_6 AIN_10 AIN_14 AIN_3 AIN_1 AIN_7 AIN_3 AIN_11 AIN_5 AIN_7 AIN_9 AIN_11 AIN_13 AIN_15 AIN_4 AIN_2 AIN_8 AIN_4 AIN_12 AIN_6 AIN_8 AIN_10 AIN_12 AIN_14 AIN_16 AIN_1 AIN_5 AIN_9 AIN_2 AIN_6 AIN_10 AIN_3 AIN_1 AIN_7 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11 AIN_4 AIN_2 AIN_8 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12 AIN_1 AIN_5 AIN_2 AIN_6 AIN_3 AIN_1 AIN_3 AIN_5 AIN_7 AIN_4 AIN_2 AIN_4 AIN_6 AIN_8 AIN_1 AIN_2 AIN_2 AIN_1 AIN_3 AIN_2 AIN_4 AIN_1 Slot 1 AIN_1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 AIN_2 LRCLK_R Right Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Slot 16 3. 10 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. The input pins I2CA0, I2CA1 and I2CA2 are used to select the slave address to which the device responds. Although the I2C system can be multi-mastered, the TVP5158 decoder functions as a slave device only. 36 Functional Description Copyright © 2009­2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TVP5158 TVP5157 TVP5156 TVP5158, TVP5157, TVP5156 www. ti. com SLES243D ­ JULY 2009 ­ REVISED OCTOBER 2010 Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are high. The slave address select terminals (I2CA0, I2CA1 and I2CA2) enable the use of up to eight devices on the same I2C bus. At the trailing edge of reset, the status of the I2CA0, I2CA1 and I2CA2 lines are sampled to determine the device address used. Table 3-16 summarizes the terminal functions of the I2C host interface. Table 3-17 shows the device address selection options. I2C Terminal Description SIGNAL I2CA0 I2CA1 I2CA2 SCL SDA TYPE I I I I/O (open drain) I/O (open drain) DESCRIPTION Slave address selection Slave address selection Slave address selection Input/output clock line Input/output data line Table 3-17. I2C Host Interface Device Addresses A6 1 1 1 1 1 1 1 1 A5 0 0 0 0 0 0 0 0 A4 1 1 1 1 1 1 1 1 A3 1 1 1 1 1 1 1 1 A2(I2CA2) 0 0 0 0 1 1 1 1 A1(I2CA1) 0 0 1 1 0 0 1 1 A0 (I2CA0) 0 1 0 1 0 1 0 1 R/W 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 HEX B1/B0 B3/B2 B5/B4 B7/B6 B9/B8 BB/BA BD/BC BF/BE Data transfer rate on the bus is up to 400 kbit/s. The number of devices connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except for start and stop conditions. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]