User manual TRANSCEND TS128MDOM44V DATASHEET

[. . . ] Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Description With an IDE interface and strong data retention ability, 44-Pin IDE Flash Modules are ideal for use in the harsh environments where Industrial PCs, Set-Top Boxes, etc. are used. Features · · · · · · · · · · · RoHS compliant products Storage Capacity: 128MB ~ 8GB Operating Voltage: 3. 3V ±5% or 5V ±10% Operating Temperature: 0° ~ 70° C C Operating Humidity (Non condensation): 0% to 95% Storage Humidity (Non condensation): 0% to 95% Endurance: 2, 000, 000 Program/Erase cycles MTBF: 1, 000, 000 hours Durability of Connector: 10, 000 times Fully compatible with devices and OS that support the IDE standard (pitch = 2. 00mm) Built-in ECC function assures high reliability of data transfer Supports up to Ultra DMA Mode 4 Supports PIO Mode 6 Support Wear-Leveling to extend product life Placement · · · Dimensions Side A B C Millimeters 52. 00 ± 0. 40 29. 50 ± 0. 50 7. 20 ± 0. 20 Inches 2. 047 ± 0. 016 1. 162 ± 0. 020 0. 284 ± 0. 008 Transcend Information Inc. 1 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Pin Assignments Pin No. Pin Name HD12 HD2 HD13 HD1 HD14 HD0 HD15 GND NC Pin Pin No Name 23 24 25 IOWB GND IORB Pin No. Pin Name Pin Definition Symbol HD0 ~ HD15 HA0 ~ HA2 -RESET IORB IOWB IOIS16B CE1B, CE2B PDIAGB DASPB DMARQ DMACKIREQ NC GND VCC Function Data Bus (Bi-directional) Address Bus (Input) Device Reset (Input) Device I/O Read (Input) Device I/O Write (Input) Transfer Type 8/16 bit (Output) Chip Select (Input) Pass Diagnostic (Bi-directional) Disk Active/Slave Present (Bi-directional) DMA request DMA acknowledge Interrupt Request (Output) No Connection Ground Vcc Power Input 01 -RESET 12 02 GND 13 03 04 05 06 07 08 09 10 11 HD7 HD8 HD6 HD9 HD5 HD10 HD4 HD11 HD3 14 15 16 17 18 19 20 34 PDIAGB 35 HA0 36 37 38 39 HA2 CE1B CE2B DASPB GND VCC VCC GND GND 26 GND 27 IORDY 28 NC 29 -DMACK 40 30 GND 41 31 IREQ 42 21 DMARQ 32 IOIS16B 43 22 GND 33 HA1 44 Pin Layout Pin1 Bulge Pin43 Pin2 Pin44 Transcend Information Inc. 2 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Block Diagram With 1 pcs of Flash Memory: With 2 pcs of Flash Memory: Transcend Information Inc. 3 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Ratings Absolute Maximum Ratings Symbol VDD-VSS Ta Tst Parameter DC Power Supply Operating Temperature Storage Temperature Min -0. 6 0 -40 Max +6 +70 +85 Unit V °C °C Recommended Operating Conditions Symbol VDD VIN Ta Parameter Power supply Input voltage Operating Temperature Min 3. 0 0 0 Max 5. 5 VDD+0. 3 +70 Units V V °C DC Characteristics (Ta=0 C to +70 C, Vcc = 5. 0V ± 10%) Parameter Supply Voltage High level output voltage Low level output voltage High level input voltage Low level input voltage o o o o Symbol VCC VOH VOL VIH VIL Min 4. 5 VCC-0. 8 -4. 0 2. 92 --- Max 5. 5 -0. 8 --0. 8 1. 70 Unit V V V V V V V Remark Non-schmitt trigger Schmitt trigger Schmitt trigger 1 Non-schmitt trigger 1 (Ta=0 C to +70 C, Vcc = 3. 3V ± 5%) Parameter Supply Voltage High level output voltage Low level output voltage High level input voltage Low level input voltage Symbol VCC VOH VOL VIH VIL Min 3. 135 VCC-0. 8 -2. 4 2. 05 --- Max 3. 465 -0. 8 --0. 6 1. 25 Unit V V V V V V V Remark Non-schmitt trigger Schmitt trigger Schmitt trigger 1 Non-schmitt trigger 1 Transcend Information Inc. 4 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Transcend Information Inc. 5 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S True IDE PIO Mode Read/Write Timing Item Mode 0 600 70 Mode 1 383 50 Mode 2 240 30 Mode 3 180 30 Mode 4 120 25 Mode 5 100 15 Mode 6 80 10 t0 t1 t2 t2 t2i t3 t4 t5 t6 t6Z t7 t8 t9 tRD Cycle time (min) 1 Address Valid to -IORD/-IOWR setup (min) -IORD/-IOWR (min) 1 -IORD/-IOWR (min) Register (8 bit) -IORD/-IOWR recovery time (min) -IOWR data setup (min) -IOWR data hold (min) -IORD data setup (min) -IORD data hold (min) -IORD data tristate (max)2 Address valid to IOCS16 assertion (max) 4 Address valid to IOCS16 released (max) 4 tA tB IORDY Pulse Width (max) tC IORDY assertion to release (max) -IORD/-IOWR to address valid hold Read Data Valid to IORDY active (min), if IORDY initially low after tA IORDY Setup time 3 165 290 -60 30 50 5 30 90 60 20 0 35 1250 5 125 290 -45 20 35 5 30 50 45 15 0 35 1250 5 100 290 -30 15 20 5 30 40 30 10 0 35 1250 5 80 80 70 30 10 20 5 30 N/A N/A 10 0 35 1250 5 70 70 25 20 10 20 5 30 N/A N/A 10 0 35 1250 5 65 65 25 20 5 15 5 20 N/A N/A 10 0 N/A 5 N/A 5 N/A 5 55 55 20 15 5 10 5 20 N/A N/A 10 0 N/A 5 N/A 5 N/A 5 Notes: All timings are in nanoseconds. [. . . ] The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions. The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred. (b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges. (c) NOTE - The host shall not immediately assert STOP to initiate Ultra DMA data burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait tRP before asserting STOP. (d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge. ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions. Transcend Information Inc. 20 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Host Terminating an Ultra DMA Data-In Burst The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions. The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra DMA data burst has been transferred. (b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall continue to negate -HDMARDY until the Ultra DMA data burst is terminated. (c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY (d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. (e) The host shall assert STOP no sooner than tRP after negating -HDMARDY. The host shall not negate STOP again until after the Ultra DMA data burst is terminated. (f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated. (g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. [. . . ] HSTROBE shall remain asserted until the Ultra DMA data burst is terminated. (f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA CRC Calculation). (g) The host shall negate -DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and -DDMARDY, and no sooner than tDVS after placing the result of its CRC calculation on D[15:00]. (h) The device shall latch the host's CRC data from D[15:00] on the negating edge of -DMACK. [. . . ]