User manual TRANSCEND TS256MSD80 QUICK INSTRUCTION GUIDE

[. . . ] The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time) total load. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met. (1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. [. . . ] d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data burst is paused, whichever occurs first. Notes: D[15:00] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Transcend Information Inc. 18 Ver 1. 2 Transcend 44-Piin IIDE Fllash Modulle Transcend 44-P n DE F ash Modu e TS128M ~ 8GDOM44V-S TS128M ~ 8GDOM44V-S Host Pausing an Ultra DMA Data-In Burst The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions. The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred. (b) The host shall pause an Ultra DMA data burst by negating -HDMARDY. (c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY. (d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. (e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY. ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. The host shall not negate STOP again until after the Ultra DMA data burst is terminated. (f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated. (g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA data burst is terminated. (h) The device shall release D[15:00] no later than tAZ after negating DMARQ. (i) The host shall drive D[15:00] no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA CRC Calculation). (j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00] during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA CRC Calculation). [. . . ] The device shall not assert -DDMARDY again until after the Ultra DMA data burst termination is complete. (e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. [. . . ]