User manual TRANSCEND TS4GJFV60

[. . . ] MIL STD Method 1009 Durability Bending Torque Drop test Visual inspection Shape and form WP Switch cycles 10. 000 mating cycles; 10N 0. 15N. m or +/-2. 5 deg 1. 5m free fall No warp page; no mold skin; complete form; no cavities surface smoothness <= -0. 1 mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc. ) minimum 1000 Cycles(@Slide force 0. 4N to 5N) Minimum moving force of WP witch 40gf (Ensures that the WP switch will not slide while it is inserted to the connector. ) Transcend Information Inc. 10 microSDHC Card series Register Information Ver1. 0 High Capacity microSD Card Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters. 1. OCR register The 32-bit operation conditions register stores the VDD voltage profile of the card. [. . . ] Additionally, this register includes 2 more status information bits. Bit 31 - Card power up status bit, this status bit is set if the card power up procedure has been finished. Bit 30 - Card capacity status bit, this status bit is set to 1 if card is High Capacity SD Memory Card. 0 indicates that the card is Standard Capacity SD Memory Card. The Card Capacity status bit is valid after the card power up procedure is completed and the card power up status bit is set to 1. The Host shall read this status bit to identify a Standard or High Capacity SD Memory Card. The OCR register shall be implemented by the cards. OCR Register Definition Transcend Information Inc. 11 microSDHC Card series Ver1. 0 High Capacity microSD Card 1) This bit is valid only when the card power up status bit is set. 2) This bit is set to LOW if the card has not finished the power up routine. A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to LOW. 2. CID Register The Card IDentification (CID) register is 128 bits wide. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate timeout and should uses fixed timeout values for read and write operations. · NSAC This field is fixed to 00h. NSAC should not be used to calculate time-out values. · TRAN_SPEED The following table defines the maximum data transfer rate per one data line - TRAN_SPEED: Transcend Information Inc. 15 microSDHC Card series Ver1. 0 High Capacity microSD Card Note that for current SD Memory Cards that field must be always 0_0110_010b (032h) which is equal to 25MHz - the mandatory maximum operating frequency of SD Memory Card. In High-Speed mode, that field must be always 0_1011_010b (05Ah) which is equal to 50MHz. And when the timing mode returns to the default by CMD6 or CMD0 command, its value will be 032h. · CCC The SD Memory Card command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this card. The COPY bit is an one time programmable bit. · PERM_WRITE_PROTECT Permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card are permanently disabled). not permanently write protected. · TMP_WRITE_PROTECT Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are temporarily disabled). not write protected. · FILE_FORMAT This field is set to 0. Host should not use this field. · CRC The CRC field carries the check sum for the CSD contents. The checksum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD contents. [. . . ] The value0x0000 is reserved to set all cards into the Stand-by State with CMD7. 5. DSR Register (Optional) The 16-bit driver stage register is described in detail in Chapter 6. 5. It can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards). The CSD register carries the information about the DSR register usage. [. . . ]