User manual ZILOG Z80 FAMILY

[. . . ] Z80 Family CPU User Manual User Manual UM008003-1202 ZiLOG Worldwide Headquarters · 532 Race Street · San Jose, CA 95126-3432 Telephone: 408. 558. 8500 · Fax: 408. 558. 8300 · www. ZiLOG. com Z80 CPU User's Manual This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408. 558. 8500 Fax: 408. 558. 8300 www. ZiLOG. com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. [. . . ] This flag is also used with logical operations and rotate instructions to indicate the resulting parity is Even. The number of 1 bits in a byte are counted. If the total is Odd, ODD parity is flagged (P = 0). If the total is Even, EVEN parity is flagged (P = 1). During search instructions (CPI, CPIR, CPD, CPDR) and block transfer instructions (LDI, LDIR, LDD, LDDR), the P/V Flag monitors the state of the UM008003-1202 Z80 Instruction Set Z80 CPU User's Manual 79 Byte Count Register (BC). When decrementing, if the byte counter decrements to 0, the flag is cleared to 0, otherwise the flag is set to1. During LD A, I and LD A, R instructions, the P/V Flag is set with the value of the interrupt enable flip-flop (IFF2) for storage or testing. When inputting a byte from an I/O device with an IN r, (C), instruction, the P/V Flag is adjusted to indicate the data parity. Half Carry Flag The Half-Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status between Bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the Decimal Adjust Accumulator instruction (DAA) to correct the result of a packed BCD add or subtract operation. The H Flag is set (1) or cleared (0) according to the following table: H Flag Add 1 0 Subtract A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs Zero Flag The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain instructions is 0. For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in the Accumulator is 0. If the byte is not 0, the Z flag is reset to 0. For compare (Search) instructions, the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the Register pair HL. When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated bit (see "Bit b, s"). UM008003-1202 Z80 Instruction Set Z80 CPU User's Manual 80 When inputting or outputting a byte between a memory location and an I/O device (INI, IND, OUTI, and OUTD), if the result of decrementing the B Register is 0, the Z flag is 1, otherwise the Z flag is 0. Also for byte inputs from I/O devices using IN r, (C), the Z flag is set to indicate a 0-byte input. Sign Flag The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When the Z80 performs arithmetic operations on signed numbers, the binary twos-complement notation is used to represent and process numeric information. A positive number is identified by a 0 in Bit 7. The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127. A negative number is represented by the twos complement of the equivalent positive number. The total range for negative numbers is from ­1 to ­128. When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S Flag indicates either positive (S = 0) or negative (S = 1) data. Z80 Instruction Description Execution time (E. T. ) for each instruction is given in microseconds for an assumed 4 MHz clock. Total machine cycles (M) are indicated with total clock periods (T States). [. . . ] Then, after the byte counter (B) is decremented, the contents of register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B may be used as a byte counter, and its decremented value is placed on the top half (A8 through A15) of the address bus at this time. Next, the byte to be output is placed on the data bus and written to the selected peripheral device. If the decremented B register is not zero, the Program Counter (PC) is decremented by two and the instruction is repeated. [. . . ]