User manual ABIT AT8 32X

[. . . ] AT8 32X AMD Athlon 64x2/64FX/64 System Board Socket 939 User's Manual 4310-0000-14 Rev. 2. 00 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] RAS# to RAS# Delay: This item specifies the RAS# active to RAS# active delay time of different bank. Write Recovery Time: This item specifies the time measured from the last write datum is safely registered by the DRAM. Write to Read Delay: This item specifies the time measured from the rising edge following the last non-masked data strobe to the rising edge of the next read command. Read to Write Delay: This item specifies the read to write delay. DRAM Command Rate: When the host (northbridge) locates the desired memory address, it then processes the wait state of commands. Bank Interleaving: Depending on your SDRAM module structure, the 4-Way setting can offer the best performance. If you choose the wrong setting, the computer system will not run in a stable manner. For detailed information on your SDRAM module, please ask your SDRAM module manufacturer. User's Manual 3-16 Chapter 3 Burst Length DDR SDRAM modules provide a Burst mode that means an auto precharge function for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. This means that if we set burst length to 8, the address bus will access 8 bytes each cycle to precharge, etc. 32 bit Dram Memory Hole: This item selects the method to remap the 32 bit Dram memory hole. Leave this item to its default "Auto" Setting. MTRR mapping mode The item selects the MTRR mapping mode. The MTRR (Memory-Type and Range Registers) controls the access and cacheability of memory regions in the processor. DRAM ECC Feature Control When installed with the DRAM that support ECC feature, you may select [ECC] option, and then control the following sub-items. ECC Memory Interlock ECC MCE Enable Chip-Kill Mode Enable ECC Redirection DRAM Scrub Rate L2 Cache Scrub Rate DCache Scrub Rate AT8 32X BIOS Setup 3-17 Back to Advanced Chipset Features Setup Menu: LDT & PCI Bus Control: Click <Enter> key to enter its submenu: Phoenix ­ AwardBIOS CMOS Setup Utility LDT & PCI Bus Control LDT Configuration Enabled Upstream LDT Bus Width 16 bit Downstream LDT Bus Width 16 bit LDT Bus Frequency Auto PCIE Reset Delay Disabled Item Help :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults LDT Configuration: This item enables or disables the LDT Configuration function. Upstream LDT Bus Width: This item sets the value for the Upstream LDT Bus Width. Downstream LDT Bus Width: This item sets the value for the Downstream LDT Bus Width. LDT Bus Frequancy: This item allows you to select LDT Bus Frequency. PCIE Reset Delay: This item enables or disables the PCIE Reset Delay function. Back to Advanced Chipset Features Setup Menu: System BIOS Cacheable: Two options are available: Disabled or Enabled. When you select Enabled, you get faster system BIOS executing speed via the L2 cache. User's Manual 3-18 Chapter 3 3-5. Integrated Peripherals Phoenix ­ AwardBIOS CMOS Setup Utility Integrated Peripherals OnChip IDE Device Press Enter OnChip PCI Device Press Enter Onboard PCI Device Press Enter Onboard FDC Controller Enabled Item Help :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults OnChip IDE Device Click <Enter> key to enter its submenu: Phoenix ­ AwardBIOS CMOS Setup Utility OnChip IDE Device IDE-1 Controller Enabled IDE-2 Controller Enabled SATA Controller Enabled Mode Selected IDE Mode ROM Enabled OnChip OnChip OnChip - SATA - SATA Item Help :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults OnChip IDE-1 Controller/ OnChip IDE-2 Controller: This item allows you to enable or disable the primary (IDE1) and secondary (IDE2) IDE controller. [. . . ] First, please contact the support team for the branch office closest to you. They will be more familiar with local conditions and will have better insight as to which resellers offer what products and services. Due to the huge number of emails coming in every day and other reasons, such as the time required for problem reproduction, we will not be able to reply to every email. Please understand that we are selling through distribution channels and while we don't have the resources to serve every end-user, we will do our best to help every customer. [. . . ]