User manual ABIT AV8

[. . . ] AV8 AMD Athlon 64TM (FX) System Board Socket 939 User's Manual 4200-0400-01 Rev. 1. 00 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] CAS Latency Time: Three options are available: 2 2. 5 3. You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM specification. RAS# to CAS# Delay: This item specifies the RAS# active to CAS# read write delay time to the same bank. RAS# Active Time: This item specifies the minimum RAS# active time. RAS# Precharge Time: This item specifies the RAS# precharge time. Row Cycle Time: This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank. Row Refresh Cycle Time: This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time. RAS# to RAS# Delay: This item specifies the RAS# active to RAS# active delay time of different bank. Write Recovery Time: This item specifies the time measured from the last write datum is safely registered by the DRAM. Write to Read Delay: This item specifies the time measured from the rising edge following the last non-masked data strobe to the rising edge of the next read command. Read to Write Delay: This item specifies the read to write delay. AV8 BIOS Setup 3-17 Back to Advanced Chipset Features Setup Menu: LDT & PCI Bus Control: Click <Enter> key to enter its submenu: Upstream/Downstream LDT Bus Width: This item allows you to select LDT Bus Width. LDT Bus Frequency: This item allows you to select LDT Bus Frequency. PCI Master 0 WS Write: Two options are available: Enabled or Disabled. When Enabled, writes to the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is set to Disabled, the system will wait one state before data is written to the PCI bus. PCI1/PCI2 Post Write: Two options are available: Enabled or Disabled. The default is Enabled, When Enable, data transmission from CPU to PCI bus are buffered and compensate for the different speed between CPU and PCI bus. If it is set to Disabled, data transmissions are not buffered and CPU must wait until the data transmission is complete and then start another transmission cycle. HT Stop Tristate: Two options are available: Driven or Tristate. The default setting is Driven. Back to Advanced Chipset Features Setup Menu: Memory Hole: When set to [15M­16M], the memory address space at 15M-16M will be reserved for ISA expansion cards that specifically requires this setting. This makes the memory from 15MB and up unavailable to the system. Vlink Data Rate: This item can let you select the Vlink Data Rate between northbridge and southbridge. [. . . ] However, we will try to do our best to help every customer. Please also remember that for many of our technical support team English is a second language, you will have a better chance of getting a helpful answer if your question can be understood in the first place. Be sure to use very, simple, concise language that clearly states the problem, avoid rambling or flowery language and always list your system components. Here is the contact information for our branch offices: AV8 How to Get Technical Support I-3 North America and South America: ABIT Computer (U. S. A. ) Corporation 45531 Northport Loop West, Fremont, California 94538, U. S. A. [. . . ]