User manual ABIT KD7A

[. . . ] KD7A Socket 462 System Board User's Manual 4200-0385-02 Rev. 1. 00 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] DRAM Clock: This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up if your DRAM module does not support the clock you set. When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM clock by the value stored in it. NOTE: This item will be unchangeable at 333MHz FSB. KD7A BIOS Setup 3-11 DRAM Timing Selectable: Four options are available: Manual By SPD Turbo Ultra. When set to "By SPD", the BIOS will read the DRAM module SPD data and automatically set to the values stored in it. If you set to "Manual", the following five items will be available to let you make adjustments. CAS Latency Time: Four options are available: 1. 5 2 2. 5 3. You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM specification. Bank Interleave: Three options are available: Disabled 2 Way 4 Way. Depending on your SDRAM module structure, the 4-Way setting can offer the best performance. If you choose the wrong setting, the computer system will not run in a stable manner. For detailed information on your SDRAM module, please ask your SDRAM module manufacturer. Precharge to Active (Trp): Trip timing value (Precharge time ­ time from precharge command to when back can be activated). Active to Precharge (Tras): Tras timing value = Minimum bank active time from activate to precharge of same bank. Active to CMD (Trcd): Trcd timing value = RAS to CAS latency + rd/wr command delay DRAM Burst Length DDR SDRAM modules provide a Burst mode that means an auto precharge function for programmable READ or WRITE burst lengths of 4 or 8 locations. This means that if we set burst length to 8, the address bus will acesss 8 bytes each cycle to precharge, etc. DRAM Command Rate: Two options are available: 2T Command or 1T Command. When the host (northbridge) locates the desired memory address, it then processes the wait state of commands. Set it to 2T Command for system compatibility or to 1T Command for system performance. Write Recovery Time: Two options are available: 2T or 3T. This is the period between two write times. DDR400 tWTR timing control Two options are available: 1T or 2T. [. . . ] However, we will try to do our best to help every customer. Please also remember that for many of our technical support team English is a second language, you will have a better chance of getting a helpful answer if your question can be understood in the first place. Be sure to use very, simple, concise language that clearly states the problem, avoid rambling or flowery language and always list your system components. Here is the contact information for our branch offices: KD7A How to Get Technical Support H-3 North America and South America: ABIT Computer (U. S. A. ) Corporation 45531 Northport Loop West, Fremont, California 94538, U. S. A. [. . . ]