User manual ABIT KV7-V

[. . . ] KV7 Series (KV7, KV7-V) AMD Athlon XP System Board Socket 462 User's Manual 4200-0380-12 Rev. 1. 01 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] AGP Pad Drive Delay: Leave this item to its default setting. AGP Strob Drive Strength: Leave this item to its default setting. KV7 Series BIOS Setup 3-13 Back to Advanced Chipset Features Setup Menu: CPU & PCI Bus Control: Click <Enter> key to enter its submenu: PCI Master 0 WS Write: Two options are available: Enabled or Disabled. When Enabled, writes to the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is set to Disabled, the system will wait one state before data is written to the PCI bus. PCI Master 0 WS Read: Two options are available: Enabled or Disabled. When Enabled, reads to the PCI bus are executed with zero wait state (immediately) when PCI bus is ready to receive data. If it is set to Disabled, the system will wait one state before data is written to the PCI bus. CPU to PCI Post Write Two options are available: Enabled or Disabled. The default is Enabled, When Enable, data transmission from CPU to PCI bus are buffered and compensate for the different speed between CPU and PCI bus. If it is set to Disabled, data transmissions are not buffered and CPU must wait until the data transmission is complete and then start another transmission cycle. Vlink 8X Support: Two options are available: Disabled or Enabled. This item can let you enable the Vlink bus data transfer between northbridge and southbridge. PCI Delay Transaction: Two options are available: Disabled or Enabled. The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2. 2. User's Manual 3-14 Chapter 3 3-5. Integrated Peripherals OnChip IDE Device: Click <Enter> key to enter its submenu: IDE Prefetch Mode: Two options are available: Disabled or Enabled. The onboard IDE drive interfaces supports IDE prefetching for faster drive accesses. If you install a primary and/or secondary add-in IDE interface, set this field to Disabled if the interface does not support prefetching. OnChip SATA Device: This option enables or disables the OnChip SATA controller. OnChip IDE-1 Controller: This item allows you to enable or disable the primary and secondary IDE controller. Select [Disabled] if you want to add a different hard drive controller. Master/Slave Drive PIO Mode The PIO (Programmed Input/Output) mode allows the BIOS to tell the controller what it wants and then let the controller and the CPU perform the complete task, rather than having the BIOS issue a series of commands to affect a transfer to or from the disk drive. [. . . ] They will be more familiar with local conditions and problems and will have better insight as to which resellers offer what products and services. Due to the huge number of emails coming in every day and other reasons, such as the time required for problem reproduction, we will not be able to reply to every email. Please understand that we are selling through distribution channels and don't have the resources to serve every end-user. However, we will try to do our best to help every customer. [. . . ]