User manual ABIT KV8-MAX3

[. . . ] KV8-MAX3 Socket 754 System Board User's Manual 4200-0389-13 Rev. 1. 02 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] [Enabled]: The system automatically detect the unused PCI slots, and stop sending clock signal to these unused PCI slots. [Disabled]: The system always send clock signal to all PCI slots. NOTE: Set this option to [Disabled] setting if there are adapters that cannot be automatically detected by the system and will cause malfunction. User's Manual 3-10 Chapter 3 3-4. Advanced Chipset Features DRAM Configuration: Click <Enter> key to enter its submenu: Current FSB Frequency: This item will show you the current system front side bus speed. Current DRAM Frequency: This item will show you the current DRAM bus speed. DRAM Timing Selectable: Two options are available: Manual By SPD. When set to "By SPD", the BIOS will read the DRAM module SPD data and automatically set to the values stored in it. DRAM Clock: This item sets the DRAM clock of your DRAM module. The system may be unstable or unable to boot up if your DRAM module does not support the clock you set. When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM clock by the value stored in it. KV8-MAX3 BIOS Setup 3-11 DRAM ECC Mode: When set to [ECC], your DRAM module will support the ECC Mode. CAS Latency Time: Three options are available: 2 2. 5 3. You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM specification. Row Cycle Time: This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank. Row Refresh Cycle Time: This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time. RAS# to CAS# Delay: This item specifies the RAS# active to CAS# read write delay time to the same bank. RAS# to RAS# Delay: This item specifies the RAS# active to RAS# active delay time of different bank. RAS# Active Time: This item specifies the minimum RAS# active time. RAS# Precharge Time: This item specifies the RAS# precharge time. Write Recovery Time: This item specifies the time measured from the last write datum is safely registered by the DRAM. Write to Read Delay: This item specifies the time measured from the rising edge following the last non-masked data strobe to the rising edge of the next read command. Read to Write Delay: This item specifies the read to write delay. User's Manual 3-12 Chapter 3 Back to Advanced Chipset Features Setup Menu: AGP & P2P Bridge Control: Click <Enter> key to enter its submenu: AGP Aperture Size: This option specifies the amount of system memory that can be used by the AGP device. [. . . ] However, we will try to do our best to help every customer. Please also remember that for many of our technical support team English is a second language, you will have a better chance of getting a helpful answer if your question can be understood in the first place. Be sure to use very, simple, concise language that clearly states the problem, avoid rambling or flowery language and always list your system components. Here is the contact information for our branch offices: KV8-MAX3 How to Get Technical Support J-3 North America and South America: ABIT Computer (U. S. A. ) Corporation 45531 Northport Loop West, Fremont, California 94538, U. S. A. [. . . ]