User manual ABIT VA-20 A5 REV 1

[. . . ] AMD AthlonTM XP / AthlonTM / DuronTM Socket 462 System Board User's Manual VA-20 Rev. 1. 00 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] DRAM Timing (Auto By SPD) Set this to the default value to enable the system to automatically set the SDRAM timing by SPD (Serial Presence Detect). SPD is an EEPROM chip on the DIMM module that stores information about the memory chips it contains, including size, speed, voltage, row and column addresses, and manufacturer. If you disable this item, you can use the following three items to manually set the timing parameters for the system memory. VA-20 BIOS Setup DRAM CAS Latency (2. 5): 3-11 Enables you to select the CAS latency time in HCLKs of 2/2 or 3/3. The value is set at the factory depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU. Bank Interleave (Disabled): Enable this item to increase memory speed. When enabled, separate memory banks are set for odd and even addresses and the next byte of memory can be accessed while the current byte is being refreshed. Precharge to Active (3T): This item is used to designate the minimum Row Precharge time of the SDRAM devices on the module. DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe (RAS) to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data lost. Tras Non-DDR400/DDR400(7T/10T): This item allows you to increase DRAM performance. Active to CMD (3T): This item specifies the minimum required delay between activation of different rows. DRAM Burst Length(4) This item describes which burst lengths are supported by the devices on the motherboard. 4-level can provide faster performance but may result in instability whereas 8-level gives the most stable but slowest performance. DRAM Command Rate (2T Command) This item enables you to specify the waiting time for the CPU to issue the next command after issuing the command to the DDR memory. We recommend that you leave this item at the default value. Press <Esc> to return to the Advanced Chipset Features page. User's Manual 3-12 Chapter 3 AGP & P2P Bridge Control Scroll to this item and press <Enter> to view the following screen: AGP Aperture Size This setting controls just how much system RAM can be allocated to AGP for video purposes. The aperture is a portion of the PCI memory address range dedicated to graphics memory address space. Host cycles that hit the aperture range are forwarded to the AGP without any translation. [. . . ] Please understand that we are selling through distribution channels and don't have the resources to serve every end-user. However, we will try to do our best to help every customer. Please also remember that for many of our technical support team English is a second language, you will have a better chance of getting a helpful answer if your question can be understood in the first place. Be sure to use very, simple, concise language that clearly states the problem, avoid rambling or flowery language and always list your system components. [. . . ]