User manual AOPEN AP5T-C2

[. . . ] : qCPUI/OqVcpuio (CPU I/O Voltage) ֤ qVcore, OqCPUpPP/MT MMX (P55C), AMD K6Cyrix 6x86L/M2, VcpuioPVcoreäۦP, VcpuioϦӵ Vio (PBSRAMChipset Voltage). : JP11 pin 11-12 Ods@N CPU , ̥i઺-Ȭ 2. 1V. ثe-ȩ|w, ҥHϥ pin 11-12 eij߰ݱz gPөΥΤTιqqL. 2-5 ww CPU INTEL P54C INTEL MMX P55C AMD K5 AMD K6-166/200 AMD K6-233 Cyrix 6x86 Cyrix 6x86L Cyrix M2 q q q q q q q q q JP11 1-2 7-8 3-4 5-6 9-10 3-4 7-8 5-6 Vcore 3. 45V 2. 8V 3. 52V 2. 9V 3. 2V 3. 52V 2. 8V 2. 9V Vio 3. 45V 3. 45V 3. 52V 3. 45V 3. 45V 3. 52V 3. 45V 3. 45V Vcpuio Vcore Vio Vcore Vio Vio Vcore Vio Vio 2. 2. 2 CPU Wv JP3 1-2 1-2 1-2 1-2 2-3 2-3 2-3 2-3 JP1 1-2 2-3 2-3 1-2 2-3 2-3 1-2 1-2 JP2 1-2 1-2 2-3 2-3 1-2 2-3 2-3 1-2 CPU -W 1. 5x (3. 5x) 2x 2. 5x (1. 75x) 3x 4x 4. 5x 5x 5. 5x Intel Pentium, Cyrix 6x86/M2 AMD K5/K6 CPU Q]-p㦳P Wv (core frequency)M~Wv (bus clock). [. . . ] бNzĤ@x˸m]master mode ñIDE1, ĤGx˸m] slave mode P˱IDE1. pGzĤTxβĥ|xШ̧DZ IDE2 masterslave mode. 2-15 ww 2 1 40 39 IDE1 2 1 40 39 IDE2 Фp: IDE Wijƽu̪iWL 46 (18-^T), HKƶǿ餣}. Фp: F̨ΪH~, ƽu̻ݪ ˸m̦n]master mode, è̷ӤUϫij Ǧw˷s˸m. IDE1 (Primary Channel) Slave (2nd) IDE2 (Secondary Channel) Master (1st) Slave (4th) Master (3rd) 2-16 ww 2. 3. 9 w LED ܿO wLEDܿOХܦ HDD LED. o-ӱưwi AΩUؤP pGҦw˪߫e- , O4-pin su , ЪW pGu 2. pin su , iHܦw1-2 3-4, Ъ`N . Pin 1 2 3 4 Description HDD LED GND GND HDD LED + + 1 2 3 4 + + 1 2 3 4 + + 1 2 3 4 HDD LED 4-pin su HDD LED 2-pin su pin 1-2 HDD LED 2-pin su pin 3-4 2. 3. 10 e-OY (Panel) e-OY20-pin ưwХܦPANEL. uYisq (power)LEDܿO, L (keylock), Suspend s , ٹq(green)LED ܿO, -s} (reset)s , z(speaker). n NQ-tEAs N "second ()", 60ns Y60-ӤQ-tE@ . O: FPM (Fast Page Mode) EDO (Extended Data Output) P줸(parity): Lparity (32 bit) Φparity (36 bit) -hWDOҳ]-p IMM Ȥ䴩 64 bit SDRAM: D eq : - 1Mx64 (8MB), 2Mx64 (16MB), 4Mx64 (32MB), 8Mx64 (64MB), 16Mx64 (128MB), - 1Mx64x2 (16MB), 2Mx64x2 (32MB), 4Mx64x2 (64MB), 8Mx64x2 (128MB), 16Mx64x2 (256MB). P줸 (parity): Lparity (64 bit) ѩ Pentium MPentium Pro Ū CPU bus 64 bit, ҥHO饲-nꦨ64 줸~tΥ`B@. 2 72-pin SIMM ƶ׬yƼe״NO64 줸, ] NDOW SIMM Ѥ 2 հOЮwBank0 MBank1. C- Bank Ҧw 4 ˪ SIMM ݨ㦳ۦPeqΫ~ॿ`B@ OPeqΫ . SIMM bP Bank WOiHQ\ Ҧp Bank0 iHO 60ns EDO, Bank1 . tê󴹤ճW檺--, -nϥΦܤ 70ns FPM DRAM ~B@ p . GƱFΪtγt , hijϥ 60ns EDO DRAMC ĵi: DOwN memory timing w]iǫΰ IJv 60nsC 70ns HW SIMM êW--Au ϥΦb~W 60MHz CPU. : EDO DRAM ]-pتbﵽOŪIJv, DzΪFPM (fast page mode), -npre-charge (Rq) , -ntri-states (j-_) X}쪺T. EDO DRAM X}|~-ӪT@oʤU@ -memoryscycle, u@欰pipe-line @, åiYu@-clock. ziHϥΦUC SIMM MDIMM HPզX覡w˦b BANK0/BANK1 DIMM Ѥ, O ]ժ-- , ̤jOeqiWL 256MB. SIMM1 None 4MB 8MB 16MB 32MB 64MB 128MB DIMM1 None 8MB 16MB 32MB 64MB 128MB 256MB SIMM2 None 4MB 8MB 16MB 32MB 64MB 128MB Subtotal of Bank0 0MB 8MB 16MB 32MB 64MB 128MB 256MB SIMM3 None 4MB 8MB 16MB 32MB 64MB 128MB DIMM2 None 8MB 16MB 32MB 64MB 128MB 256MB SIMM4 None 4MB 8MB 16MB 32MB 64MB 128MB Subtotal of Bank1 0MB 8MB 16MB 32MB 64MB 128MB 256MB Size of DIMM1 0MB 8MB 16MB 32MB 64MB 128MB 256MB Size of DIMM2 0MB 8MB 16MB 32MB 64MB 128MB 256MB 2-22 ww Total Memory Size = Subtotal of Bank0 + Subtotal of Bank1 + Size of DIMM1 + Size of DIMM2 -OҲեut@--- DOu䴩| RAS# H (Row . address latch, O), C@ RAS#Hu䴩@ RAMҲ, Lk@ ² D . Bank1 DIMM2 㦳P--. Bank0 DIMM1 u঳@- Ҳ, t@-ӥŤU . Bank1 DIMM2 u঳@- Ҳ, t@-ӥŤU . UiHM Ъ`N Bank0 Ĥ@-DIMM1 ĤG-ϥάۦPRAS0#. ziHϥγ- SIMM Bank0, - DIMM DIMM1. Ou@--ҲեiH mBank0 DIMM1. Bank0 1st side RAS0# RAS1# RAS2# RAS3# X X X X X X X Bank0 2nd side Bank1 1st side Bank1 2nd side DIMM1 1st side DIMM1 2nd side X DIMM2 1st side DIMM2 2nd side Фp: P@BankSIMM P@DΤjp. Фp: @DIMMϥ EDO FPMOIC, L-̥u ϥ5Vq, ӥBLkJDODIMMѤ. [. . . ] Yes, . ĵi: ϥ16M by 4 bit chip (64M bit ޳N) 64MB SIMM ثeb-WäM, åBg AOpen ճ . Ъ`Nϥ16M by 1 bit chip (16M bit ޳N) 64MB SIMM WL24IC, jPij-n ϥ. Ҧpϥ1M by 4 bit chip -SIMM 1Mx32 bit, Y1M x 4 byte= 4MB. pG O- SIMM, u-n-2 Yi, p8MB. 2-26 ww UCX ij SIMM DIMM զX: SIMM Data chip 1M by 1 1M by 1 1M by 4 4M by 1 4M by 1 16M by 1 16M by 1 SIMM Parity chip None 1M by 1 1M by 1 None 4M by 1 None 16M by 1 C- bit ƥ 4Mx64 4Mx64 16Mx64 16Mx64 x1 x2 x1 x2 C- bit ƥ 1Mx32 1Mx36 1Mx36 4Mx32 4Mx36 16Mx32 16Mx36 - - x1 x1 x2 x1 x1 x1 x1 Chip ƥ 32 36 24 32 36 32 36 SIMM jp 4MB 4MB 8MB 16MB 16MB 64MB 64MB ijP_ No No No No No No No DIMM Data chip 4M by 4 4M by 4 16M by 4 16M by 4 Chip ƥ 16 32 16 32 DIMM jp 32MB 64MB 128MB 256MB ijP_ No No No No DOϥparity 覡O~. [. . . ]