User manual AOPEN AP5TC

[. . . ] AP5TC User's Guide Printed in Taiwan PART NO. : 49. 87907. 001 DOC. : AP5TC-1-E9801A AP5TC Mainboard User's Guide Document Number Model and Revision Manual Version Release Date : AP5TC-1-E9801A : For AP5TC revision 1. xx : English, revision A : Jan 9, 1998 More help for latest information: Taiwan USA Europe http://www. aopen. com. tw http://www. aopen-usa. com http://www. aopenamerica. com http://www. aopen. nl Copyright Copyright © 1998 by this company. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, manual or otherwise, without the prior written permission of this company. ii Disclaimer This company makes no representations or warranties, either expressed or implied, with respect to the contents hereof and specifically disclaims any warranties, merchantability or fitness for any particular purpose. Any software described in this manual is sold or licensed "as is". [. . . ] Which means the 2nd, 3rd and 4th memory cycles are 2 CPU clocks for EDO and 3 clocks for FPM. The value of x is the timing of first memory cycle and depends on the "DRAM Leadoff Timing" setting. Chipset Features à DRAM Write Burst Timing DRAM Write Burst Timing x444 x333 x222 Write Burst means to write four continuous memory cycles on four predefined addresses to the DRAM. This item sets the DRAM write timing of the 2nd, 3rd and 4th memory cycles. There is no difference of EDO and FPM DRAM on the write burst timing. The value of x depends on the "DRAM Leadoff Timing" setting. Chipset Features à Fast EDO Lead Off Fast EDO Lead Off Enabled Disabled This item enables fast EDO read timing, results 1 clock pull-in for read leadoff latency of EDO read cycles. It must be Disabled, if any FPM DRAM is installed. Chipset Features à Refresh RAS# Assertion Refresh RAS# Assertion 5 Clks 4 Clks This item controls the number of clocks RAS is asserted for refresh cycle. 3-13 AWARD BIOS Chipset Features à DRAM Page Idle Timer DRAM Page Idle Timer 2 Clks 4 Clks 6 Clks 8 Clks This item determines the amount of time in CPU clocks that DRAM page will be close after CPU becomes idle. Chipset Features à DRAM Enhance Paging DRAM Enhance Paging Enabled Disabled When Enabled, TX chipset will keep DRAM page open as long as possible according to enhanced method. Chipset Features à SDRAM (CAS Lat/RAS-to-CAS) SDRAM(CAS Lat/RAS-to-CAS) 2/2 3/3 These are timing of SDRAM CAS Latency and RAS to CAS Delay, calculated by clocks. They are important parameters affects SDRAM performance, default is 2 clocks. If your SDRAM has unstable problem, change 2/2 to 3/3. Chipset Features à SDRAM Speculative Read SDRAM Speculative Read Enabled Disabled Enable this item reduce one clock of SDRAM read leadoff timing by presenting the SDRAM read request before the controller chip decodes the final memory target. This Item must be Disabled if more than one DIMM is installed in the system. Chipset Features à System BIOS Cacheable System BIOS Cacheable Enabled Disabled Enabling this item allows you to cache the system BIOS to further enhance system performance. 3-14 AWARD BIOS Chipset Features à Video BIOS Cacheable Video BIOS Cacheable Enabled Disabled Allows the video BIOS to be cached to allow faster video performance. Chipset Features à 8 Bit I/O Recovery Time 8 Bit I/O Recovery Time 1 2 3 4 5 6 7 8 NA For some old I/O chips, after the execution of an I/O command, the device requires a certain amount of time (recovery time) before the execution of the next I/O command. Because of new generation CPU and mainboard chipset, the assertion of I/O command is faster, and sometimes shorter than specified I/O recovery time of old I/O devices. This item lets you specify the delay of 8-bit I/O command by count of ISA bus clock. If you find any unstable 8-bit I/O card, you may try to extend the I/O recovery time via this item. If set to NA, the chipset will insert 3. 5 system clocks. Chipset Features à 16 Bit I/O Recovery Time 16 Bit I/O Recovery Time 1 2 3 4 NA The same as 16-bit I/O recovery time. This item lets you specify the recovery time for the execution of 16bit I/O commands by count of ISA bus clock. If you find any of the installed 16-bit I/O cards unstable, try extending the I/O recovery time via this item. If set to NA, the chipset will automatically insert 3. 5 system clocks. 3-15 AWARD BIOS Chipset Features à Memory Hole At 15M-16M Memory Hole At 15M-16M Enabled Disabled This option lets you reserve system memory area for special ISA cards. The chipset accesses code/data of these areas from the ISA bus directly. Normally, these areas are reserved for memory mapped I/O card. Chipset Features à PCI Passive Release PCI Passive Release Enabled Disabled This item lets you control the Passive Release function of the PIIX4 chipset (Intel PCI to ISA bridge). This function is used to meet latency of ISA bus master. Try to enable or disable it, if you have ISA card compatibility problem. Chipset Features à PCI Delayed Transaction PCI Delayed Transaction Enabled Disabled This item lets you control the Delayed Transaction function of the PIIX4 chipset (Intel PCI to ISA bridge). This function is used to meet latency of PCI cycles to or from ISA bus. Try to enable or disable it, if you have ISA card compatibility problem. Chipset Features à Mem. [. . . ] Check if you have a Legacy ISA card (non PnP). If yes, set the IRQ and DMA for this card to Legacy/ISA. Refer to Chapter 3 "PCI/PnP Setup" section. If you are using a PnP operating system such as Win95, enable the "Plug-and-Play Aware O/S" parameter in BIOS and let the OS configure the system. [. . . ]