User manual AOPEN AP5VM-AMI

[. . . ] Chapter 3 AMI BIOS This chapter tells how to configure the system by setting the BIOS parameters. 3. 1 Entering the AMI BIOS Setup . The AMI BIOS Setup Main Menu To enter the AMI BIOS Setup, press appears as shown below. The AMI BIOS is in Windows form. You can use either the keyboard or a mouse to move between the items. To select among the Setup menu groups, use to highlight the selected group or simply click on the icon of the selected Setup menu. [. . . ] FAST MA TO RAS# DELAY This option specifies the wait state between the master address (MA) and row address strobe (RAS) signals. The selections are 1 clock and 2 clocks. EDO:SPM READ BURST TIMING This parameter adjusts the read wait state for Extended Data Out (EDO) DRAM and Standard Page Mode (SPM) DRAM. Every time the CPU reads the second-level cache miss, it reads four continuous memory cycles on four continues addresses from the EDO and SPM cache. The selections for this parameter are x444/X444, X333/X444, X222/X333, and X3222/X333. The value of X depends on the DRAM Lead-off Timing parameter setting. DRAM WRITE BURST TIMING This parameter adjusts the write wait state between the second-level and the DRAM cache. The second-level cache is processed through write-back method and each cache write process consists of four continuous cache write cycles. The parameter settings are X444, X333, and X222. Faster DRAMs require shorter wait states. The value of X depends on the DRAM Lead-off Timing parameter setting. FAST RAS TO CAS DELAY This option specifies the wait state between the row address strobe (RAS) and column address strobe (CAS) signals. The available settings are 3 clocks and 2 clocks. DRAM LEAD-OFF TIMING This option specifies the DRAM waiting time or the delay before data can be accessed. Some DRAMs may require a longer delay to access data. The selections are 11-7-3, 10-6-3, 11-7-4, and 10-6-4. 3-13 AMI BIOS Utility REFRESH RAS# ASSERTION This function controls the number of clocks required to assert RAS# for refresh cycles. The available settings are 4 clocks and 5 clocks. FAST EDO PATH SELECT Enable this option to select a fast path for CPU to DRAM read cycles to minimize the lead-off time. For other DRAM types, we recommend that you set this to Disabled. SDRAM CAS# LATENCY This parameter controls the wait state between SDRAM row address strobe and SDRAM CAS signals. SDRAM RAS# TIMING This parameter controls the RAS# precharge, RAS# active-to-precharge time, and refresh-to-RAS# active signal delay. 8-bit I/O Recovery Time (Sysclk) This parameter allows you to set the response time of the 8-bit I/O devices connected to your system. The settings range from 1-8 SYSCLK and Disabled. 16-bit I/O Recovery Time (Sysclk) This parameter allows you to set the response time of the 16-bit I/O devices connected to your system. The settings range from 1-4 SYSCLK and Disabled. ISA Clock Divisor This option specifies the ISA bus clock divisor. [. . . ] Select No to keep your current settings. 3-28 AMI BIOS Utility 3. 5. 3 Turbo When you select Turbo, a dialog box prompts you to load the Turbo values to further enhance system performance. Select No to keep your current settings. In case your system operation becomes unstable and incompatibility problems occur, unload the Turbo values and 3-29 AMI BIOS Utility 3. 6 Exiting Setup Carefully check your new settings when you have finished configuring the system. If correct, write them down and keep the recorded values in a safe place. [. . . ]