User manual ASROCK P67 TRANSFORMER

[. . . ] P67 Transformer User Manual Version 1. 0 Published December 2010 Copyright©2010 ASRock INC. All rights reserved. 1 Copyright Notice: No part of this manual may be reproduced, transcribed, transmitted, or translated in any language, in any form or by any means, except duplication of documentation by the purchaser for backup purpose, without written consent of ASRock Inc. Products and corporate names appearing in this manual may or may not be registered trademarks or copyrights of their respective companies, and are used only for identi cation or explanation and to the owners' bene t, without intent to infringe. Disclaimer: Speci cations and information contained in this manual are furnished for informational use only and subject to change without notice, and should not be constructed as a commitment by ASRock. ASRock assumes no responsibility for any errors or omissions that may appear in this manual. [. . . ] Debug is used to provide code information, which makes troubleshooting even easier. Please see the diagrams below for reading the Dr. Debug codes. Status Code 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C ­ 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D ­ 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 Description Not used Power on. Reset type detection (soft/hard) AP initialization before microcode loading North Bridge initialization before microcode loading South Bridge initialization before microcode loading OEM initialization before microcode loading Microcode loading AP initialization after microcode loading North Bridge initialization after microcode loading South Bridge initialization after microcode loading OEM initialization after microcode loading Cache initialization Reserved for future AMI SEC error codes Microcode not found Microcode not loaded PEI Core is started Pre-memory CPU initialization is started Pre-memory CPU initialization (CPU module speci c) Pre-memory CPU initialization (CPU module speci c) Pre-memory CPU initialization (CPU module speci c) Pre-memory North Bridge initialization is started Pre-Memory North Bridge initialization (North Bridge module speci c) Pre-Memory North Bridge initialization (North Bridge module speci c) Pre-Memory North Bridge initialization (North Bridge module speci c) Pre-memory South Bridge initialization is started Pre-memory South Bridge initialization (South Bridge module speci c) Pre-memory South Bridge initialization (South Bridge module speci c) Pre-memory South Bridge initialization (South Bridge module speci c) OEM pre-memory initialization codes Memory initialization. Serial Presence Detect (SPD) data reading Memory initialization. Memory presence detection Memory initialization. Programming memory timing information Memory initialization. Con guring memory Memory initialization (other) Reserved for ASL (see ASL Status Codes section below) Memory Installed CPU post-memory initialization is started CPU post-memory initialization. Cache initialization CPU post-memory initialization. Application Processor(s) (AP) initialization CPU post-memory initialization. Boot Strap Processor (BSP) selection CPU post-memory initialization. System Management Mode (SMM) initialization 29 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F-0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C-0x5F 0xE0 0xE1 0xE2 0xE3 0xE4-0xE7 0xE8 0xE9 0xEA 0xEB 0xEC-0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5-0xF7 0xF8 0xF9 0xFA 0xFB ­ 0xFF 0x60 0x61 Post-Memory North Bridge initialization is started Post-Memory North Bridge initialization (North Bridge module speci c) Post-Memory North Bridge initialization (North Bridge module speci c) Post-Memory North Bridge initialization (North Bridge module speci c) Post-Memory South Bridge initialization is started Post-Memory South Bridge initialization (South Bridge module speci c) Post-Memory South Bridge initialization (South Bridge module speci c) Post-Memory South Bridge initialization (South Bridge module speci c) OEM post memory initialization codes DXE IPL is started Memory initialization error. Invalid memory type or incompatible memory speed Memory initialization error. SPD reading has failed Memory initialization error. Invalid memory size or memory modules do not match Memory initialization error. No usable memory detected Unspeci ed memory initialization error Memory not installed Invalid CPU type or Speed CPU mismatch CPU self test failed or possible CPU cache error CPU micro-code is not found or micro-code update is failed Internal CPU error reset PPI is not available Reserved for future AMI error codes S3 Resume is stared (S3 Resume PPI is called by the DXE IPL) S3 Boot Script execution Video repost OS S3 wake vector call Reserved for future AMI progress codes S3 Resume Failed S3 Resume PPI not Found S3 Resume Boot Script Error S3 OS Wake Error Reserved for future AMI error codes Recovery condition triggered by rmware (Auto recovery) Recovery condition triggered by user (Forced recovery) Recovery process started Recovery rmware image is found Recovery rmware image is loaded Reserved for future AMI progress codes Recovery PPI is not available Recovery capsule is not found Invalid recovery capsule Reserved for future AMI error codes DXE Core is started NVRAM initialization 30 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A ­ 0x7F 0x80 ­ 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E ­ 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 Installation of the South Bridge Runtime Services CPU DXE initialization is started CPU DXE initialization (CPU module speci c) CPU DXE initialization (CPU module speci c) CPU DXE initialization (CPU module speci c) CPU DXE initialization (CPU module speci c) PCI host bridge initialization North Bridge DXE initialization is started North Bridge DXE SMM initialization is started North Bridge DXE initialization (North Bridge module speci North Bridge DXE initialization (North Bridge module speci North Bridge DXE initialization (North Bridge module speci North Bridge DXE initialization (North Bridge module speci North Bridge DXE initialization (North Bridge module speci South Bridge DXE initialization is started South Bridge DXE SMM initialization is started South Bridge devices initialization South Bridge DXE Initialization (South Bridge module speci South Bridge DXE Initialization (South Bridge module speci South Bridge DXE Initialization (South Bridge module speci South Bridge DXE Initialization (South Bridge module speci South Bridge DXE Initialization (South Bridge module speci ACPI module initialization CSM initialization Reserved for future AMI DXE codes OEM DXE initialization codes Boot Device Selection (BDS) phase is started Driver connecting is started PCI Bus initialization is started PCI Bus Hot Plug Controller Initialization PCI Bus Enumeration PCI Bus Request Resources PCI Bus Assign Resources Console Output devices connect Console input devices connect Super IO Initialization USB initialization is started USB Reset USB Detect USB Enable Reserved for future AMI codes IDE initialization is started IDE Reset IDE Detect IDE Enable SCSI initialization is started SCSI Reset c) c) c) c) c) c) c) c) c) c) 31 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 ­ 0xBF 0xC0 ­ 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC SCSI Detect SCSI Enable Setup Verifying Password Start of Setup Reserved for ASL (see ASL Status Codes section below) Setup Input Wait Reserved for ASL (see ASL Status Codes section below) Ready To Boot event Legacy Boot event Exit Boot Services event Runtime Set Virtual Address MAP Begin Runtime Set Virtual Address MAP End Legacy Option ROM Initialization System Reset USB hot plug PCI bus hot plug Clean-up of NVRAM Con guration Reset (reset of NVRAM settings) Reserved for future AMI codes OEM BDS initialization codes CPU initialization error North Bridge initialization error South Bridge initialization error Some of the Architectural Protocols are not available PCI resource allocation error. Out of Resources No Space for Legacy Option ROM No Console Output Devices are found No Console Input Devices are found Invalid password Error loading Boot Option (LoadImage returned error) Boot Option is failed (StartImage returned error) Flash update is failed Reset protocol is not available 32 2. 11 Serial ATA (SATA) / Serial ATAII (SATAII) Hard Disks Installation This motherboard adopts Intel® P67 chipset that supports Serial ATA (SATA) / Serial ATAII (SATAII) hard disks and RAID (RAID 0, RAID 1, RAID 10, RAID 5 and Intel Rapid Storage) functions. You may install SATA / SATAII hard disks on this motherboard for internal storage devices. This section will guide you to install the SATA / SATAII hard disks. STEP 1: Install the SATA / SATAII hard disks into the drive bays of your chassis. STEP 2: Connect the SATA power cable to the SATA / SATAII hard disk. STEP 3: Connect one end of the SATA data cable to the motherboard's SATAII connector. [. . . ] Boot Failure Guard Enable or disable the feature of Boot Failure Guard. Boot Failure Guard Count Enable or disable the feature of Boot Failure Guard Count. 57 3. 7 Security Screen In this section, you may set or change the supervisor/user password for the system. For the user password, you may also clear it. 58 3. 8 Exit Screen Save Changes and Exit When you select this option, it will pop-out the following message, "Save con guration changes and exit setup?" Select [OK] to save the changes and exit the UEFI SETUP UTILITY. Discard Changes and Exit When you select this option, it will pop-out the following message, "Discard changes and exit setup?" Select [OK] to exit the UEFI SETUP UTILITY without saving any changes. [. . . ]