User manual ASUS E500-PI

[. . . ] ® CUSL2-M Intel® 815E microATX Motherboard USER'S MANUAL USER'S NOTICE No part of this manual, including the products and software described in it, may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means, except documentation kept by the purchaser for backup purposes, without the express written permission of ASUSTeK COMPUTER INC. ASUS PROVIDES THIS MANUAL "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL ASUS, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF BUSINESS, LOSS OF USE OR DATA, INTERRUPTION OF BUSINESS AND THE LIKE), EVEN IF ASUS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES ARISING FROM ANY DEFECT OR ERROR IN THIS MANUAL OR PRODUCT. Product warranty or service will not be extended if: (1) the product is repaired, modified or altered, unless such repair, modification of alteration is authorized in writing by ASUS; or (2) the serial number of the product is defaced or missing. [. . . ] Refer to your drive documentation or look on the drive for this information. If no drive is installed or if you are removing a drive and not replacing it, select [None]. Translation Method [LBA] Select the hard disk drive type in this field. When Logical Block Addressing is enabled, 28-bit addressing of the hard drive is used without regard for cylinders, heads, or sectors. Note that LBA Mode is necessary for drives with greater than 504MB in storage capacity. Configuration options: [LBA] [LARGE] [Normal] [Match Partition Table] [Manual] Cylinders This field configures the number of cylinders. Refer to your drive documentation to determine the correct value to enter into this field. NOTE: To make changes to this field, the Type field must be set to [User Type HDD] and the Translation Method field must be set to [Manual]. BIOS SETUP Head This field configures the number of read/write heads. Refer to your drive documentation to determine the correct value to enter into this field. NOTE: To make changes to this field, the Type field must be set to [User Type HDD] and the Translation Method field must be set to [Manual]. Sector This field configures the number of sectors per track. Refer to your drive documentation to determine the correct value to enter into this field. NOTE: To make changes to this field, the Type field must be set to [User Type HDD] and the Translation Method field must be set to [Manual]. CHS Capacity This field shows the drive's maximum CHS capacity calculated automatically by the BIOS from the drive information you entered. Maximum LBA Capacity This field shows the drive's maximum LBA capacity calculated automatically by the BIOS from the drive information you entered. Multi-Sector Transfers [Maximum] This option automatically sets the number of sectors per block to the highest number supported by the drive. This field can also be configured manually. Note that when this field is automatically configured, the set value may not always be the fastest value for the drive. Refer to the documentation that came with your hard drive to determine the optimal value and set it manually. NOTE: To make changes to this field, the Type field must be set to [User Type HDD]. Configuration options: [Disabled] [2 Sectors] [4 Sectors] [8 Sectors] [16 Sectors] [32 Sectors] [Maximum] SMART Monitoring [Disabled] This allows the enabling or disabling of the S. M. A. R. T. [. . . ] SCSI (Small Computer System Interface) High speed multi-threaded I/O interface defined by the X3T9. 2 committee of the American National Standards Institute (ANSI) for connecting many peripheral devices. The standard started from 10MBytes/sec to 160MBytes/sec available today. SDRAM (Synchronous DRAM) The SDRAM features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables the coexistence of high performance and a simple user interface. SDRAM takes memory access away from the CPU's control; internal registers in the chips accept the request, and let the CPU do something else while the data requested is assembled for the next time the CPU talks to the memory. [. . . ]