User manual CADENCE DESIGN SYSTEMS ALLEGRO FPGA SYSTEM PLANNER DATASHEET

[. . . ] Often the pin assignment for these FPGAs is done manually at a pin-by-pin level in an environment that is unaware of the placement of critical PCB components that are connected to FPGAs. Without understanding the impact to PCB routing, FPGA-based design projects are forced to choose between two poor options: live with suboptimal pin assignment, which can increase the number of layers on a PCB design; or deal with several unnecessary iterations at the tail end of the design cycle. Even with several iterations, this manual and error-prone approach can result in unnecessary PCB design re-spins. With the added time required to generate pin assignments for FPGAs using manual approaches, users are unable to do tradeoffs between the different FPGA devices available and the cost of devices used in an FPGA sub-system. [. . . ] Users can create interfaces such as DDR2, DDR3, and PCI Express, and use these to specify connectivity between a FPGA and a memory DIMM module or between two FPGAs. The Allegro FPGA System Planner understands differential signals, and power signals, as well as clock signals. Allegro Part Library Symbols, Footprints Figure 3: The Allegro FPGA System Planner uses symbols and footprints from existing libraries FPGA DeViCe ruLeS The Allegro FPGA System Planner comes with a library of device-accurate FPGA models that incorporate pin assignment rules and electrical rules specified by FPGA device vendors. These FPGA models are used by the synthesis engine to ensure that the vendor-defined electrical usage rules of the FPGAs are strictly adhered to. These rules dictate such things as clock and clock region selection, bank allocation, SSO budgeting, buffer driver utilization, I/O standard voltage reference levels, etc. During synthesis, the Allegro FPGA System Planner automatically checks hundreds of combinations of these rules to ensure that the FPGA pins are optimally and accurately utilized. used for the signals that are assigned to the FPGA pins. As a result, users have to make several iterations between the spreadsheet-based tools and the tools from FPGA vendors. Often this adds an increased number of iterations between the PCB layout designer who cannot route the signals from FPGA pins on available layers and the FPGA designer who has to accept paper-based or verbal pin-assignment suggestions from the PCB layout designer. Once a change is made to the pin assignment by the FPGA designer, the pin assignment change has to be made in the schematic design by the hardware designer. Such iterations add several days if not weeks to the design cycle and possibly a great deal of frustration for the team members. Since this is a manual process, mistakes that are not detected can also cause expensive physical prototype iterations. While it may help to automate the synchronization of changes made to the pin assignment by the FPGA designer, hardware designer, or PCB layout designer, it doesn't reduce the root cause of these iterations. Pin assignment that is not guided by all three aspects--FPGA resource availability, FPGA vendor pin assignment rules, and routability of FPGA pins on a PCB--requires many iterations at the tail end of the design process, thereby extending the time it takes to integrate today's complex, large-pin-count FPGAs on a PCB. SPeCiFYinG DeSiGn inTenT The Allegro FPGA System Planner comes with an FPGA device library to help with selection of devices to be placed. It uses OrCAD PCB Designer or Allegro PCB Editor footprints for the floorplan view and allows users to quickly create relative placement of the FPGA system components. The Allegro FPGA System Planner allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface Figure 4: The Allegro FPGA System Planner optimizes multiple FPGAs concurrently www. cadence. com C ADE nCE AllEG ro FPGA Sy STEm PlA nn Er 3 PLACeMenT AWAre Pin ASSiGnMenT SYnTHeSiS The Allegro FPGA System Planner provides users a way to create an FPGA system placement view using Allegro PCB footprints. Users specify connectivity between components in the placement view and the FPGA at a high level using interfaces such as DDRx, PCI Express, SATA, Front Side Bus, etc. that connect FPGAs and other components in the design, shortening the time to specify design intent for the FPGA system. Once the connectivity of the FPGA to other components in the sub-system is defined, the Allegro FPGA System Planner then synthesizes the pin assignment based on the user's design intent, available FPGA resources, component placement around the FPGA, and the FPGA vendor's pin assignment rules. The Allegro FPGA System Planner has a built-in DRC engine that incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations. [. . . ] Manual pin assignment approaches make performing these cost and performance trade-offs very time consuming and tedious. With its placement-aware FPGA I/O pin assignment synthesis, the Allegro FPGA System Planner helps designers do trade-offs quickly, enabling architectural exploration that is not practical with manual approaches. OrCAD FPGA System Planner Concurrent device optimization Placement-aware synthesis Reuse symbols and footprints Symbols & schematic generation Post-placement optimization Schematic power connections Schematic terminations 1 FPGA Yes Yes OrCAD Capture No No No Allegro FPGA System Planner L 1 FPGA Yes Yes Allegro FPGA System Planner Two FPGA Option 2 FPGAs Yes Yes Allegro FPGA System Planner XL 4 FPGAs Yes Yes Allegro FPGA System Planner GXL Unlimited FPGAs Yes Yes Allegro Design Entry Allegro Design Entry Allegro Design Entry Allegro Design Entry CIS / Allegro Design CIS / Allegro Design CIS / Allegro Design CIS / Allegro Design Entry HDL Entry HDL Entry HDL Entry HDL Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes www. cadence. com C ADE nCE AllEG ro FPGA Sy STEm PlA nn Er 4 TiGHT inTeGrATiOn WiTH CADenCe DeSiGn CreATiOn The Allegro FPGA System Planner generates Allegro Design Entry CIS and Allegro Design Entry HDL schematics for the FPGA sub-system. It uses existing symbols for FPGA in Allegro Design Entry symbol libraries. If the user desires, the Allegro FPGA System Planner can create split symbols for FPGA based on the connectivity or one split symbol per bank. hardware designer. [. . . ]