User manual CADENCE DESIGN SYSTEMS CADENCE ANALOG OVERVIEW

[. . . ] The Cadence AMS Design Methodology combines the best of top-down (behavioral and mixed-level approaches) with bottom-up (transistor-level design and abstraction) design techniques to achieve predictable, high-quality results for complex mixedsignal designs. AMS DESIGN METHODOLOGY The Cadence AMS Design Methodology delivers an extensive design and data flow guide, from design specification through design manufacturing, across the different functions of a design team. It is based on executable design tasks and recommended use models for fast, silicon-accurate mixed-signal design that ensures first-pass silicon success. The AMS Design Methodology addresses the analog-driven mixed-signal design process front to back by executing well-defined flows that demonstrate a meetin-the-middle approach, in which all design flows are running in parallel to minimize design iterations, maximize project resource utilization, and enhance design quality. [. . . ] This part of the Cadence AMS Design Methodology gives the foundation to set up a design environment using tested and proved methods and technologies, including incremental tool access, project directory structure, how to set up and control PDKs, and how to automate project and flow setup using the Design Environment and Configuration Manager. The data exchange between the design house and the foundry is explained, detailing required datasets from the foundry and how to qualify them against the defined AMS flows. Special attention is given to the PDK--how to automatically check its content using the Data Surveyor and how to use the Incremental Technology Database (ITDB) to customize and enhance the PDK /projects/ ProjectA/ ProjectB/ ProjectC/ TOP-DOWN FUNCTIONAL VERIFICATION A comprehensive functional verification flow is presented, spanning all levels of abstraction and all design stages, from planning to post-layout device-level signoff verification. First, an introduction to the concept of design partitioning and simulation planning is given. Next, behavioral modeling guidelines and testbench strategies are presented. A consistent testbench structure is used over all later stages of verification, starting with concept validation using behavioral model representation in AMS simulation, and system validation using Simulink/AMS co-simulation. Next is performance validation using mixed-level-transistor plus behavioral-level simulation on Virtuoso AMS Designer Simulator with SDF backannotated to the digital part. Finally, a post-layout and signoff verification is prepared to include both analog extracted parasitics and SDF backannotation for the most accurate timing estimation using Virtuoso AMS-Ultra Simulator. An IDDQ analysis is performed using full extracted transistor-level DC simulation with the Virtuoso UltraSim Full-Chip Simulator along with top-level EM IR drop analysis. deslibs/ doc/ Project Documents Design libraries user1/ user2/ . cdsinit Working libraries . cds. lib assura_tech. lib display. drf . csdenv hdl. var Figure 4: AMS design environment and infrastructure Figure 5: AMS top-down functional verification www. cadence. com CADENCE ANALOG/MIXED-SIGNAL DESIGN METHODOLOGY 3 AMS IP BLOCK CREATION AND REUSE A thorough approach to creation of both analog and digital blocks is presented using productivity-oriented Virtuoso technology. The constraints concept and management is used to amend the schematic with the required information to automatically create its layout. Furthermore, constraints can be inferred from pre-defined circuit structures using the Circuit Prospector Assistant. New layout techniques like design-rule­driven (DRD), module generator (Modgen), and constraint-driven editing are shown in action through a dedicated assisted layout module. A new approach to simulation is shown through the specification-oriented simulation platform (Virtuoso Analog Design Environment) with its numerous productivity enhancement features including simulation history, check points manager, parameterization flow, design specifications, and parasitic estimation flow. The high-capacity Virtuoso Analog Design Environment optimization engine is used for local and global optimization on the block level, over corners, and as a yield optimizer with Monte Carlo and sensitivity analyses. AMS IP EXPORT AND INTEGRATION The IP flow is a comprehensive guide for analog and digital IP handling, from top-level integration to extensive characterization and packaging. On the exporting side, a complete step-by-step scenario of characterizing and modeling an analog IP in Verilog®AMS is presented, taking an N-bit flash ADC as an example. Automated testbench extraction is discussed; generic behavioral model planning, coding, and debugging is illustrated. [. . . ] This is possible through a Virtuoso Floorplanner, a Physical Hierarchy Configurator, and an Abstract Generator, along with several floorplanning techniques like connectivity analysis, area estimation, pushdown block shaping, and pin optimization. The analog-oriented physical assembly and routing is described using both Virtuosos Chip Assembly Router and Virtuoso SpaceBased Router, both accepting design constraints. The flow is demonstrated by top-level routing of the Ethernet PHY and the PLL macro using advanced analog routing techniques like critical signal, differential signal, shielded signal, bundle, and supply routing. [. . . ]