User manual CADENCE DESIGN SYSTEMS CADENCE C-TO-SILICON COMPILER DATASHEET

[. . . ] CADEnCE C-To-SiLiCon CompiLER HiGH-LEVEL SYnTHESiS DATASHEET C-to-SiliCon Compiler C-to-Silicon Compiler increases new design productivity and significantly eases legacy design reuse by starting design at a high level of abstraction. [. . . ] integrated with the Encounter digital iC implementation flow, C-to-Silicon Compiler uses full-context, gate-level timing feedback from embedded logic synthesis to rapidly achieve the desired results. Embedded logic synthesis also ensures that the generated RTL will synthesize exactly as predicted. C-to-Silicon Compiler is the first high-level synthesis technology to deliver four critical capabilities in one package: · Embedded logic synthesis (ELS) enables parallel optimization of control and datapath logic, delivering better-than-average human quality of results (QoR) · Behavior-structure-timing (BST) database enables true incremental synthesis and much faster design and verification turnaround time · Constraint-functionality separation (CFS) enables reuse across multiple applications and process technologies · Auto-generated fast hardware models (FHMs) accelerate verification and enable hardware/software co-development Hardware architects and RTL designers can use these capabilities to: C-to-Silicon Compiler tracks each design change and its area/performance impact at every design level, enabling comprehensive design space exploration. Designers can quickly and easily iterate multiple, different RTL micro-architecture options to identify the optimum micro-architecture with the desired area and timing QoR. technology in C-to-Silicon Compiler strictly separates the functional description from design constraints. Separate synthesis directive files guide C-to-Silicon Compiler toward different implementations, ensuring that the original function model remains "golden. " perform faster, more reliable verification The patent-pending FHm generation technology in C-to-Silicon Compiler creates cycle-accurate FHms, functionally equivalent to the RTL that simulate in the incisive simulation environment 80­90% as fast as the original untimed input model. These FHms enable faster verification and earlier hardware-software co-design. execute engineering change orders with minimum effort other high-level synthesis tools force designers to re-synthesize the entire design whenever any change is made. C-to-Silicon Compiler incremental synthesis enables designers to implement changes and engineering change orders (ECos) incrementally, without disturbing the rest of the design, and avoid repeating their entire design/verification flow on the whole design. BenefitS · Enablescontrolanddatapath micro-architecture exploration to determine optimum design tradeoffs · Providesearlierfeedbackon implementation feasibility, area, and performance · Createsbetter-than-manual­qualityRTL for new designs with much less effort · PerformsfastECOswithoutfull re-synthesis and re-verification · Easilyretargetsdesignsfor different applications and manufacturing processes · Acceleratesdesignclosurewithfar fewer iterations · Enablesfastersimulation and verification · Allowsengineerstodevelopsoftware earlier with FHm virtual prototype optimize results for the broadest possible set of designs other high-level synthesis tools typically analyze control logic and datapath logic separately, and fail to produce sufficiently accurate timing estimates, forcing engineers to design the two types of logic separately and integrate them manually. C-to-Silicon Compiler analyzes and synthesizes both control logic and datapath logic together, and it performs the tradeoffs necessary to achieve the optimum area and performance. maximize design reusability Conventional high-level synthesis tools require implementation-specific pragmas, synthesis directives, and extensions to be embedded in the input source code, making it difficult to reuse for different implementations. [. . . ] All others are properties of their respective holders. [. . . ]