User manual CADENCE DESIGN SYSTEMS CADENCE CHIP OPTIMIZER DATASHEET

[. . . ] CAD E n CE CHI p O p T I m I z E r Design contraints Advanced manufacturing constrains DATASHEET CadenCe Chip Optimizer Cadence Chip Optimizer provides unique interconnect optimization capabilities that improve yield, manufacturability and timing closure during design. [. . . ] Cadence Chip Optimizer uses a patented three-dimensional, space-based approach to model and analyze true shapes and intervening physical spaces. It allows shapes and spaces to be positioned in the exact configuration and location required to correct sub-wavelength manufacturing effects. This capability affords greater precision and flexibility when optimizing the interconnects while using tiered design and manufacturing constraints. A common misconception is that these manufacturing and design objectives are always in opposition. However there is often a mutually agreeable solution. By optimizing wires (space and width), for example, designers can reduce the probability of opens and shorts (which is good for yield) while also reducing coupling capacitance (which is good for signal integrity, timing and power). With the powerful analysis and topology optimization capabilities provided by Cadence Chip Optimizer, designers can quickly achieve convergence that addresses both manufacturing and design objectives. ­ Works seamlessly with the Cadence Encounter and the Virtuoso platforms ­ Works with third-party implementation flows through industry-standard interfaces ­ runs natively on OpenAccess features manufaCturabilitY and Yield enhanCements · Optimizesviastoreduceviafailuresdue to process window variability or misalignment. Enhancements include total via count reduction, adding multiple vias, optimizing enclosures and spacing · Optimizeswirestoreducewirefailures due to isolated lines (opens) or minimum spaced lines (shorts) · Optimizesmetaltominimizechemical mechanical polishing (Cmp) effects · Eliminatesprocessantennas · IncreasesmanufacturabilityandRET efficiency by optimizing wire topologies manufaCturing and design ClOsure manufacturers and designers have different objectives. Fabs want designs to adhere to design for manufacturing (DFm) and design for yield (DFY) rules and recommendations for their advanced process nodes. [. . . ] all others are properties of their respective holders. [. . . ]