User manual CADENCE DESIGN SYSTEMS CADENCE IC DATASHEET

[. . . ] Electrical constraints are signal delay and distortion specifications for critical nets. Designs can be dynamically checked against these constraints throughout the design process to ensure they are meeting manufacturing and electrical specifications. Immediate feedback is provided by way of DRC markers as well as flagging violations in the spreadsheet-based Constraint Manager. reducing cycle time on future designs. Substrate suppliers can provide tech files that typically contain critical design rules to help drive a correct design methodology. [. . . ] Manual workarounds that address multi-user challenges are time consuming, slow, and prone to error. The design partitioning technology provides a multi-user, aUtoMatIC BUMP-to-PaCkage PIn assIgnMent and RoUte FeasIBIlIty Nearest-match, router-based, or constraint-driven algorithms determine best routable assignment based on existing design rules. Nets are assigned by layers based on net constraints and route channel availability. Differential pairdefined bumps are automatically assigned adjacent package pins accordingly. A hIgh densIty InteRConneCt (hdI) desIgn HDI or build-up layer technology is pervasive in almost all IC Package design using routable organic substrates and fine pitch flipchip devices. All levels of Allegro Package Designer and Allegro Package SI have comprehensive constraint-driven HDI design capabilities linked to automation-assisted interactive design. Comprehensive microvia class Figure 3: Constraint-driven HDI design allows designers to rapidly implement complex via structures www. ca de nce . com CA D ENC EI C /PAC KA G EC O -DESI G N 3 or Allegro PCB SI format. These capabilities compress setup time and increase data accuracy for systems designers. Co-desIgn FeatURes (avaIlaBle In allegRo PaCkage desIgneR Xl) Cadence IC/package co-design technology enables concurrent co-design between IC and package, allowing designers of today's complex, leading-edge devices to meet cost, performance, and time-tomarket goals. They can now perform electrical and physical feasibility studies and make IC/package design tradeoffs early in the design phase, before implementation decisions are made and options become limited. Die abstract and package substrate co-design reduces package complexity and optimizes substrate performance and cost. Users can now determine the best package and substrate technology early in the IC design cycle. The co-design technology also provides chip-levelI/Oplanningcapabilitiesand functionalities targeted at streamlining theengineeringchangeorder(ECO)flow between IC and package design. Based onLEF/DEForOpenAccessprotocols(the standard formats for IC data exchange), it includes a robust set of import/export capabilities, enabling IC and package designers to send die abstract changes back and forth. This reduces design time and allows users to realize an optimized IC die padring/array, bump matrix, and package substrate. Figure 4: Plating bar support includes intelligent recognition of etchback interconnect such that metal is made available to manufacturing output, but appropriately ignored when analyzing design data concurrent design methodology for faster time to market and reduction in layout time. Using this technology, multiple designers working concurrently on a layout share access to a single database, regardless of team proximity. Design partitioning technology allows designers to partition designs into multiple sections or areas for layout and editing by several design team members. The partitioning can be vertical (cake slice) or horizontal (layer based). As a result, each designer can view all partitioned sections and update the design view for monitoring the status and progress of other users' sections. This can dramatically reduce overall design cycles and accelerate the design process. Users can easily create bond diagrams, dimension documents, format drawings, and various output files containing critical package data. Manufacturing output supportsGerber4X00and6X00series, 274X, Barco, DXF, AIF2, andGDSII. (See Figure 4. ) Many package foundries currently use Cadence IC/package co-design technology. This pervasiveness allows users to send an Allegro design database directly to the foundry as manufacturing input, greatly compressing throughput times and preempting potential inaccuracies. [. . . ] It manages tasks such as matched lengths, phase control for differential pairs, impedance, or delay rules. (See Figure 8. ) an IntellIgent 3d desIgn vIeW Virtually all of today's technologies for fabric physical layout--IC, IC package, or PCB--are two-dimensional. While ideal for substrate layout, interconnect planning, and metal fill creation, this "planview" process does not lend itself well to the design, management, and verification of complex die stack towers. The design complexity and density involved require a morerealisticapproach. TheCadence3D Design Viewer meets this need by providing an IC package designer with the ability to physically visualize a design as it will actually look during manufacture. [. . . ]