User manual CADENCE DESIGN SYSTEMS CADENCE PCB SIGNAL AND POWER INTEGRITY DATASHEET

[. . . ] Designers can also accurately address shrinking timing budgets by considering the effects of package design on the overall performance of the signal from die to die. The integrated flow is of great value to the designers, who now can easily perform pre- and post-layout extraction and verification of complex high-speed PCB systems. KEY CAPABILITIES · Highlyintegrateddesignandanalysis environment removes the need for error-prone and time-consuming design translation. · Pre-routeanalysisdesignmethodology streamlines post-route design verification through a consistent front-to-back constraint management system. · Powerstabilityanddeliveryare optimized through DC and AC power analysis. [. . . ] Allegro PCB SI includes static IR drop (DC) analysis technology that verifies that the power distribution system can provide sufficient current to drive signals. The analysis considers effects due to trace neck-down; Swiss-cheese planes created by components with dense pin grid arrays; and reduction of available copper caused by trace routing on power and ground planes. The analysis also takes into account all vias that connect multiple ground planes of the same net. Results can be viewed in a graphical voltage drop www. ca de nce . com CA D EnC E PCB SI g n A L An D Po wER I n TEg RI Ty 2 display (See Figure 3. ) or in a report that shows voltage drop at any pin that is marked as a current sink. Users can also view relative and absolute voltage drop at any point on the net. AC power integrity is accomplished with Allegro PCB PI, an option to Allegro PCB SI. Its unique, integrated design and analysis environment takes the guesswork out of quantifying and controlling noise in power delivery systems. Engineers can focus on the design instead of struggling with data translation issues between the CAD system and the analysis engines. Allegro PCB PI integrates proven technology from Sun Microsystems into the Cadence design and analysis environment to address the power delivery issues encountered in high-speed design. Frequency domain simulation allows users to quantify the impedance of the power delivery system across the frequency range of interest. In addition, the effectiveness of the decoupling capacitor selection and placement can be verified in the time domain, where ripples in the voltages can be measured and optimized. Chip current profiles accurately characterize a target impedance in Allegro PCB PI. In addition, capacitance on the chip and inductance from the package, or package and die power delivery models, can be assigned to an arbitrary position on a two-dimensional plane structure on the board to perform frequency or time domain simulations. Figure 3: Static IR drop can be performed within the same user interface as signal integrity analysis. Engineers can verify power delivery and signal quality from a single environment. With CDR Without CDR SERIAL LINK DESIGN METHODOLOGY when engineers face today's demands for faster data throughput, each section of the interface takes on greater complexity. Transceivers feature dynamic equalization and clock and data recovery algorithms that require advanced modeling techniques. S-parameters for IC package models must be used to accurately characterize interconnect from the die to the package pin. And PCB structures must be carefully characterized such that signal loss, frequency-dependent materials, and impedance discontinuities are all accurately represented through broadband s-parameter interconnect models. Figure 4: Multi-gigabit serial links can be confirmed to be electrically compliant with interface standards such as PCI Express 2. 0 through the use of eye masks, algorithmic transceiver models (IBIS-AMI), and high-capacity (million-bit) simulation. The Allegro PCB SI solution features integrated field solvers (including 2D full-wave FEM), support for the IBIS 5. 0 algorithmic model interface (AMI) standard for describing SerDes signal processing, and accurate analytical via modeling (narrowband, wideband, s-parameter). Allegro PCB SI is a uniquely integrated and accurate solution for serial link design and compliance testing. [. . . ] Singleor coupled-net EMI simulation along with a comprehensive rule-checking engine, EMControl, enables engineers to design for EM compliance. Users can create, manipulate, and validate models quickly in an easy-to-use editing environment. Support is available for IBIS, Spectre, Mentor/Quad XTK, and Synopsys HSPICE (requires HSPICE simulator and license, which is not included with Allegro PCB SI). Engineers can evaluate placement strategies with this floorplanning option--used in conjunction with design logic authoring tools--and assign design intent by embedding constraints in the front-end design database. [. . . ]