User manual CADENCE DESIGN SYSTEMS CADENCE PHYSICAL VERIFICATION SYSTEM DATASHEET
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Manual abstract: user guide CADENCE DESIGN SYSTEMS CADENCE PHYSICAL VERIFICATION SYSTEMDATASHEET
Detailed instructions for use are in the User's Guide.
[. . . ] CAD En C E PH yS I C A L V ERi fi C At i o nS yS t E m
DATASHEET
The Cadence Physical Verification System delivers integration with industry-standard digital and custom design flows, enabling designers to procure a front-to-back design and signoff flow from a single EDA vendor. PVSalsofacilitatesa"onetool, onedeck"modelfordigitalandcustom design that minimizes support overhead. [. . . ] This allows PVS users to leverage their existing investment in rule decks and infrastructure with no requirement for translationorscripts. Ruledecksexecute natively on PVS, and PVS reports design errors in an intuitive, predictable and familiar way, which greatly accelerates tool and flow validation and integration.
FEATURES
CompETiTivE pERFoRmAnCE mAinTAinS dESign ThRoUghpUT
PVS delivers single-processor performance that is highly competitive with other industry-leading physical verification solutions. Large designs can also take advantage of the unique operation-based distributed processing architecture that leverages low-cost, off-the-shelf compute platforms to greatly accelerate design throughput.
bEnEFiTS
· Single-vendorsolutionfor implementation and back-end signoff · Rapiddesignturnaroundwith production-proven accuracy · Simplifiesmigrationthroughdirect compatibility with industry-standard formats
inTEgRATion wiTh EnCoUnTER And viRTUoSo plATFoRmS ACCElERATES dESign dEbUg
PVS is seamlessly integrated with the Cadence Encounter® digital design platform and the Virtuoso® custom design platform. It also operates in CDB and Open Access environments. This means designers can invoke PVS and browse PVS error markers without leaving their Cadence design environment. PVS also runs standalone in batch mode, and supports CadenceQRCparasiticextractionflows.
PVS features the industry's first Verilog®compatible netlist-based LVS debug capability. An interface with a highperformance, high-capacity design viewer enables PVS users to efficiently debug very large SoC designs with design file sizes in the tens of gigabytes range. [. . . ] All others are properties of their respective holders. [. . . ]
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