User manual CADENCE DESIGN SYSTEMS INCISIVE VERIFICATION KIT DATASHEET

[. . . ] INCISIVE VERIFICATION KIT ENABLING METRIC-DRIVEN VERIFICATION DATASHEET VERIFICATION CHALLENGES Functional verification challenges have never been so great. With ASICs now in the multi-million gate range, verification engineers need to generate and manage thousands of tests, deal with frequent changes to the specification and project plan, and coordinate multiple teams/ sites. [. . . ] The environment contains verification methodologies and flows, a realistically challenging reference design, and an advanced metric-driven verification methodology. It also integrates many components from the Cadence portfolio of reusable verification IP (sold separately). The kit can be leveraged to develop your own environment, or can be a learning tool with its interactive design/verification navigator and integrated Cadence "CDNS Help" system. KIT BENEFITS · Acceleratesandeasesadoptionofnew verification technologies and methodologies · Increasespredictabilitybyautomating the verification management and analysis process · Improvesverificationproductivityby demonstrating how to maximize verification throughput (optimal coverage per cycle) · Reducesriskandensuresquality through realistic golden verification examples · Testbenchanddesignsbasedonstandard OVM languages: e, SystemVerilog, SystemC®, as well as Verilog® and VHDL · Showshow-toandbestpracticeswith easy-to-follow hands-on labs productivity of their verification process and, ultimately, the quality of their design. The Incisive Verification Kit demonstrates the methodologies and capabilities in the form of workshops, hands-on labs, and tutorial documentation, with the ability to automatically invoke the needed Incisive tool or VIP. The kit addresses the verification of both hardware and device software KIT COMPOSITION AND INTEGRATION The Incisive Verification Kit demonstrates multiple verification flows on an OpenCores RISC processor design. The platform consists of both Cadence and third-party IP integrated using AMBA® APB, AHB, AXI, and multi-layer AHB bus fabrics. The kit contains documented best practices and "golden" executable verification plans. There are two levels of the kit, both of which are supplied with Incisive Enterprise Simulator: the IP-level kit for IP creators and the SoC-level kit for SoC creators. Both the IP and SoC kits use Cadence Verification IP or Universal Verification Components (UVCs). UVCs provide pre-built verification, from executable plans to protocol compliance management, enabling metricdriven verification out of the box and significantly accelerating your verification productivity. POWERFUL WORKSHOPS AND LABS Cadence has assembled all of its functional verification workshops and labs and aggregated them into a single kit-based environment. [. . . ] AMBA is a registered trademark of ARM, Ltd. All others are properties of their respective holders. [. . . ]