User manual CADENCE DESIGN SYSTEMS LOW-POWER METHODOLOGY KIT DATASHEET

[. . . ] CADEnCE Low-PowEr METHoDoLogy KIT tu re Consulting IP DATASHEET introduCtion Ever-increasing device integration, as well as the need for advanced mobile applications, is driving the need to reduce power consumption across a wide range of design types (wireless, networking, and consumer). [. . . ] Verification throughout all stages is critical since advanced power management techniques have significant functional impact on the design. Meeting the power consumption and density requirements of modern electronic devices means engineers must consider power at all stages of the design process--from architecture through implementation. If not done properly, however, adding advanced power management to an already complex design process significantly increases project costs and risks. The Cadence Low-Power Methodology Kit enables design and implementation teams to streamline the adoption of low-power techniques, optimize their usage, and get predictable results with minimal risk. Low-Power Techniques App M licability Multiple voltage thresholds, low-power clocking multiple supply voltages, power shut-off odolog eth y Design Creation Architecture, RTL, CPF, synthesis, DFT Verification Functional, implementation power-grid sign-off Planning, metrics, ECO Management Infrastructure, process selection, library qualification Design Environment Segment Representative Design CadenCe Low-Power MethodoLogy Kit The Cadence Low-Power Methodology Kit provides users with a complete front to back methodology for low-power implementation and verification. It combines industry-leading Cadence lowpower technology from the Incisive and I n fra s t r uc Physical Implementation Prototyping, parasitics, floorplanning, timing and SI closure Encounter platforms, with a single power specification format (CPF) and proven methodologies. It captures best practices in the form of executable flows, as well as detailed checklists that ensure a high level of automation and a clean handoff between different tasks and groups within the design team. The kit is highly modularized Multiple Threshold Voltage Low Power Clocking Multiple Supply Voltages (MSV) Power Shut Off (PSO) Architecture Trade-off RTL Design CPF Creation Low Power Synthesis Power Aware DFT Prototyping and Parasitics Correlation Power Planning Low Power Floorplanning Timing and SI Closure Power Grid Sign-off Low Power Implementation Verification Low Power Functional Verification Infrastructure Process Selection Library Qualification Process Selection Library Qualification · Detailed low-power methodology guide, covering all aspects of lowpower implementation · reference flow implementations with step-by-step walkthroughs · Detailed documentation of the SrD and reference flow · Detailed flow checklists, and trade-off analysis · Expert consulting designed to map the verified and demonstrated methodologies to a specific customer design The Low-Power Methodology Kit utilizes and integrates with the following technologies (not included) · Cadence Logic Design Team Solution · Incisive Plan-To-Closure Methodology · Incisive Enterprise Family · Incisive Formal Verifier · Encounter rTL Compiler · Encounter Test · First Encounter · SoC Encounter · Encounter Conformal EC · Encounter Conformal LP · Voltage Storm to allow for incremental adoption and to allow teams to focus on what is most critical for the design. [. . . ] Cadence is a registered trademark and the Cadence logo is a trademark of Cadence design Systems, inc. [. . . ]