User manual CADENCE DESIGN SYSTEMS MEMS CO-DESIGN METHODOLOGY OVERVIEW

[. . . ] CADENCE MIXED-SIGNAL / MEMS CO-DESIGN METHODOLOGY OVER VIEW · MEMSdesign · Mixed-signaldesign MEMS IP MEMS Inter-Digitized Sensor Clock Tree C-to-V Signal Proc ADC As more micro-electro-mechanical systems (MEMS) are being used for automotive and consumer electronics, engineers need a robust MEMS and mixed-signal co-design flow that enables both system-on-chip (SoC) and systemin-package (SiP) approaches. A clear-cut interface between a MEMS design subflow and the conventional mixed-signal sub-flow is necessary. [. . . ] This decreases the entry barrier for the mixedsignal design team to integrate the MEMS structure. In addition, most of the steps that require handling by the mixed-signal designer (due to the presence of the MEMS structure) are handled from the SIMPLI cockpit. Thus, the mixed-signal designer will not need special training on the MEMS design sub-flow. FEATURES MIXED-SIGNAL / MEMS SPECIFICATION-DRIVEN ENVIRONMENT · EnablesverificationIPreuse Required MEMS IP Input Files Functional Description Files GDSII Files Specification Files Measurement Files LEF Files · Automatesverificationtasks · Testingenvironmentcanbehierarchical · Usemodelcanbesimilartodigitalfunctionalverification Target PDK SIMPLI Library Processor Assura Customization · Performsco-optimizationandRFsimulationformixed-signal/ MEMS designs Specifications captured as expressions, waveforms, or , post-processing scripts Symbol View Symbol Generation CDL Netlist Testbench bank and simulation analysis definition Layout View Layout Generation Specification boundaries Layout GDSII File DRC Abstract View Coupled C Extraction Spice Black-Box Spectre Black-Box Spice, Spectre Coupled C Netlists Global variables Abstract Generation CDL Black-Box Abstract LEF Files Blackboxing Encrypted Functional File Functional View Auxiliary Virtuoso not shipped Functional View Figure 3: SIMPLI interface handles MEMS IP publishing and importing Figure 4: Specification-driven environment using Virtuoso technology www. cadence. com CADENCE MIXED-SIGNAL / MEMS CO-DESIGN METHODOLOGY 2 SIMPLI INTERFACE DEDICATED TO MEMS DOMAIN One challenge in the co-design of MEMS and mixed-signal portions of a chip is that they might not necessarily be sharing the same flow. Moreover, the information required by the mixedsignal design team might not be readily available from the MEMS tools. An extra layer is necessary to automate the generation of all the necessary information from the MEMS tools while still allowing IP protection. The Cadence Mixed-Signal / MEMS Co-Design Methodology uses a SIMPLI interface dedicated to the MEMS domain. SIMPLI is a type of VCAD productivity IP that operates on standard inputs and generates views required for mixed-signal design within the Cadence Design Framework. Moreover, SIMPLI automates the extraction of parasitic coupling capacitances at the interface with thereleasedMEMSstructure. UsingtheSIMPLIinterface, designers have the flexibility to export their layout as an abstract view, and their behavioral or reduced-order models in a 128-bit RSA encrypted format, while ensuring that the information is useful for simulation by the mixed-signal design group. SIMPLI run mode: · Release - for MEMS designer to release a MEMS component · Integration - for SoC designer to integrate a MEMS Paramerterizable accelerometer suitable for both simulation optimization and schematicdriven layout System output Accelerometer mechanical inputs stimuli through inherited connections Switched-cap sampling clock Figure 6: Early co-simulation of the full chip, including the MEMS PCELL-DRIVEN MIXED-SIGNAL / MEMS PHYSICAL CO-DESIGN The Mixed-Signal / MEMS Co-Design Methodology demonstrates a Pcell approach for laying out complicated MEMS structures, such as accelerometers. Early design-rule checks (DRC) are implemented directly in the Pcell. A motion-aware Pcell is demonstrated for the purpose of electrical parasitic extraction of the MEMS structure. [. . . ] Cadence, the Cadence logo, Assura, and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. . [. . . ]