User manual CADENCE DESIGN SYSTEMS SPACE-BASED ROUTER DATASHEET

[. . . ] CAD E n CE S pACE - B AS E D R ou T E R DATASHEET CadenCe Routing teChnology The physical implementation process-- including routing--is what can make or break your yield and manufacturing objectives. [. . . ] Its unique routing architecture is based on a patented space-based approach that meets the manufacturing, lithography, materials, and performance requirements of high-end digital and analog/mixed-signal designs. The router works seamlessly within both the Virtuoso® custom design and Encounter® digital design platforms for maximum productivity and quality of silicon. As designers integrate more and more digital and analog/mixedsignal content into single chips, they face critical effects on yield and manufacturability, such as growing lithography issues, inconsistent manufacturing rules, copper materials, electrical concerns, and performance requirements. Cadence® Space-Based Router addresses all of these concerns simultaneously, helping designers achieve shorter time to convergence, better quality of silicon, and differentiated products for consumer and wireless markets. Virtuoso custom design platform Third-party custom design implementation Encounter digital IC design platform Third-party custom design implementation Design and electrical constraints OpenAccess LEF/DEF Cadence Space-Based Router 45/65nm block and chip assembly routing system Cadence Chip Optimizer Electrical optimization Yield optimization Advanced manufacturing constraints Signoff to manufacturing Figure 1: Cadence Space-Based Router's architecture incorporates electrical and manufacturing constraints to achieve optimal quality of results for mixed-signal and high-performance designs CadenCe SPaCe-BaSed RouteR Cadence Space-Based Router is a siliconproven, three-dimensional, hierarchical, grid-less, space-based, full-chip and block routing convergence system for advanced mixed-signal, analog, and custom digital designs at 65nm and below. Its constraint-driven, interactive/automatic physical design interconnect environment offers a streamlined flow, from constraint definition and routing through analysis/ verification and refinement. The router models advanced processes and design constraints, providing maximum control and exceptional results upfront in the design process for highperformance blocks and full chips. It also features specialty mixed-signal routing, incremental in-core electrical analysis, and design-for-manufacturing and design-foryield optimization. Cadence Space-Based Router improves the design's manufacturability and reduces time-consuming post-processing for opC and copper planarity issues, ensuring that you meet your manufacturing and electrical objectives the first time around. You can specify advanced constraints for high-performance routing such as sophisticated wire tapering, layer control, and noise avoidance. [. . . ] all others are properties of their respective holders. [. . . ]