User manual CADENCE DESIGN SYSTEMS VIRTUOSO ANALOG DESIGN ENVIRONMENT GXL DATASHEET

[. . . ] VIRTUOSO ANALOG DESIGN ENVIRONMENT GXL DATASHEET VIRTUOSO CUSTOM DESIGN PLATFORM When design objectives dictate manipulating precise analog quantities-- voltages, currents, charges, and continuous ratios of parameter values such as resistance and capacitance--companies turn to custom design. Full-custom design maximizes performance while minimizing area and power. [. . . ] The Virtuoso custom design platform accelerates the design of custom ICs across various process nodes. By selectively automating aspects of custom analog design and providing advanced technologies integrated on a common database, it allows engineers to focus on precision-crafting their designs--without sacrificing creativity to repetitive manual tasks. entry into the analysis process with easy entry and execution of simulations. Analog Design Environment XL extends the L tier capabilities, providing multiple test support, analysis over sweeps, corners, and Monte Carlo, and easy reviewing of all results, either directly or as a datasheet. Analog Design Environment GXL builds on the Analog Design Environment L and XL capabilities by providing targeted tools that aid with key design challenges with early parasitic analysis, design centering, and designing in multi-technologies. VIRTUOSO ANALOG DESIGN ENVIRONMENT The Virtuoso Analog Design Environment product suite provides all the capabilities required to fully explore, analyze, and verify a design against the user's desired goals. As the industry's leading solution for analog simulation control and management, it allows users to flexibly select the tier that best supports their design goals as they move through the design flow. Analog Design Environment L provides a quick VIRTUOSO ANALOG DESIGN ENVIRONMENT GXL OVERVIEW Virtuoso Analog Design Environment GXL uses the same advanced design and simulation cockpit as Analog Design Environment XL and includes extended analysis capabilities for more detailed design exploration. A user can choose to launch Analog Design Environment GXL directly or just access the additional analysis capabilities from Analog Design Environment XL. BENEFITS · Extendeddesignexplorationwith Sensitivity and Mismatch analysis · Advancedoptimizationalgorithms improve design centering and yield · Built-inparasiticestimationflowhelps to quickly identify parasitic sensitivities prior to layout · Supportformultipletechnologiesto facilitate multi-chip design analysis · Modelcalibrationandvalidation support for Verilog® A and Verilog AMS languages · GeneratesLibertyandWrealmodels from simulation results for system-level simulation Virtuoso Analog Design Environment GXL: Extends analysis into parasitic and yield FEATURES EXTENDED ANALYSIS To further understand the behavior of a design, users can run Sensitivity analysis to identify weaknesses in a design to process variations and for design sizing. Built upon the statistical analysis capabilities in Analog Design Environment XL, Mismatch analysis can be used to further explore the sensitivities of a design against the mismatch over all or a selected set of devices. DESIGN CENTERING With the setup of tests and specifications already available in Analog Design Environment XL, users can simply add the ranges of devices they want to explore and use Analog Design Environment GXL optimization engines to find the optimum design. With an array of local and global optimization choices available, the user can control how the optimizer runs to center a design over nominal, all defined corners and with parasitic estimates in place. A and Verilog AMS with full calibration, while users can also create models from parametric data in Verilog D, Liberty, and Wreal model formats. PARASITIC RESIMULATION Users can explore parasitic effects early in the design flow with the ability to assign parasitic estimates onto nets and ports of their design, without editing the schematic. An estimated View is compiled for simulation across all the tests and analysis options available in Analog Design Environment XL or GXL to identify areas to focus on in the design development. Similarly, post-layout extracted designs can also be submitted for validation against the design goals or compared against the original parasitic estimates. Parasitic effects can be easily copied from an extracted view back to an estimated view to gain full access to all the debug capabilities in Analog Design Environment. DESIGN FOR YIELD Designers can use a series of both global and local optimization methods to center their design values to help maximize yield. [. . . ] Cadence, the Cadence logo, Allegro, Verilog and Virtuoso are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. [. . . ]