User manual CADENCE DESIGN SYSTEMS VIRTUOSO CHIP ASSEMBLY ROUTER DATASHEET

[. . . ] VIR T u oS o C H I P A S S E M B LY R ouT E R Figure 1: All components of the Virtuoso platform work together to support fast, silicon-accurate differentiated custom silicon G0007A DATASHEET The vIRTUOSO cUSTOm deSIgn plaTfORm When design objectives dictate manipulating precise analog quantities--voltages, currents, charges, and continuous ratios of parameter values such as resistance and capacitance--companies turn to custom design. Full-custom design maximizes performance while minimizing area and power. [. . . ] The Virtuoso Chip Assembly Router is interoperable with both the Virtuoso custom design platform and the Cadence Encounter® digital IC design platform. A unique blend of interactive and automatic design constraint- and process rule-driven routing features are provided, simplifying the most complex interconnect issues and maximizing productivity. The Virtuoso Chip Assembly Router supports 90nm and above process technology rules and is available on openAccess. BenefITS · Increased productivity and design quality through the specification and adherence of complex constraint and process rules during interactive and automatic routing · Simplified routing process using advanced features such as interactive push and shove, multi-net/bus, power, shielding, differential pairs, length, and crosstalk (see Figure 2) · Intuitive, easy-to-use interface with menu, command, and `do' file use options · open and flexible interoperability with the Virtuoso Schematic Editor and Virtuoso XL Layout Editor to support dynamic cross-probing and editing (see Figure 3). Interoperability with the SoC EncounterTM system is also supported Figure 2: Interactive and automatic bus and power routing Figure 3: Real-time interoperability with the Virtuoso Schematic Editor and the Virtuoso XL Layout Editor to provide accurate and accelerated block and chip design V I R Tu o S o C H IP ASSEMBLY R ouTER w w w. c a d e n ce. com feaTUReS deSIgn cOnSTRaInT and pROceSS RUle-dRIven ROUTIng The Virtuoso Chip Assembly Router accelerates the design process by providing a comprehensive set of design constraints and process rules that are specified, managed, and obeyed in a hierarchical precedence order during interactive and automatic routing. Dynamic real-time checking is performed during interactive routing with a halo display and automatic enforcement of the rules (see Figure 4). Automatic routing rules are obeyed during routing with optional post-route checking of the entire design or selective areas of the design. Figure 4: Interactive routing uses connectivity-, constraint-, and design-rule­driven features with push and shove for fast and accurate editing advanced InTeRacTIve ROUTIng feaTUReS The Virtuoso Chip Assembly Router simplifies the routing process with advanced interactive and automatic routing features. Interactive routing provides push and shove routing that eliminates the need to move other adjacent routing obstructions. Multi-net/bus routing supports the routing of two or more nets to efficiently route large bus structures. Power is fully automated with pin-to-trunk, cell row, block ring, I/o ring, and stripes/mesh features. flexIBle SUppORT cUSTOm BlOck and chIp ROUTIng The Virtuoso Chip Assembly Router simplifies the adoption and implementation of its unique custom block and chip routing solution with an intuitive and easy-to-use interface. [. . . ] cadence, encounter, virtuoso, and Sourcelink are registered trademarks and the cadence logo and Soc encounter are trademarks of cadence design Systems, Inc. all others are properties of their respective holders. [. . . ]