User manual CADENCE DESIGN SYSTEMS VIRTUOSO LAYOUT SUITE FAMILY DATASHEET

[. . . ] And finally, Virtuoso Layout Suite GXL is a robust set of advanced automated design tools that satisfy demanding physical design tasks such as automatic placement, routing, and optimization. The Virtuoso Layout Suite is built on the fully featured connectivity- and constraintdriven environment that is at the core of the Virtuoso platform. These technologies are the fundamental building blocks for generating first-time correct and optimal silicon. FEATURES HIERARCHICAL, MULTI-wINDOw, MULTI-TABBED, INTUITIVE EDITING ENVIRONMENT The Virtuoso Layout Suite enables users to open multiple cells or blocks in a single editing session, or different views of the same design, to ensure consistency in complex designs. users can also open and manage their designs more quickly by using tabs, bookmarks, and history. [. . . ] Context-sensitive menus and double-click operations allow for rapid operations on selected results. The World View Assistant is an intuitive navigational aide that allows users to see the entire design even while zoomed-in to a specific section of layout. This is particularly useful when working with large layouts where users have to perform editing while zoomed-in on a portion of the design. Being able to concentrate on a specific section of layout, while still having the full layout context available, decreases the need for repetitive panning and zooming. This translates into fewer mouse clicks, which improves layout productivity. and managed with variable settings, thus improving layout productivity while reducing design-rule violations. DOCkED LAYOUT ASSISTANTS Docked assistants are user interface widgets that surround the main layout editing canvas. Within the Virtuoso Layout Suite are a rich set of assistants including a Design Navigator, Property Editor, Search, and World View that enhance layout productivity. Through the Design Navigator Assistant, users can quickly and efficiently access specific cells that may be in a lower level of the design hierarchy via a built-in tree HIGHLY CUSTOMIzABLE EDITING ENVIRONMENT The architecture and implementation of the Cadence Design Framework ii (DFii) based on the openAccess database allow the Virtuoso Layout Suite to have a usercustomizable layout editing environment and features. This is made possible throughthesupportoftheflexibleand industry-proven SKiLL programming language. SKiLL provides direct access to the design database and tools to meet the custom design requirements of any design methodology or process technology. Additionally, the openAccess database supports a C++/C-based APi and toolbox to enable tool customization and interoperability. CONNECTIVITY-DRIVEN CAPABILITIES AND FLOw Driven by a schematic connectivity source using Virtuoso Schematic Editor or a netlist source such as CDL or SPiCE, the Virtuoso Layout Suite generates an LVS-correct layout using correctby-construction methods to improve productivity and shorten verification time. Tedious design tasks can be automated, such as device generation, placement, and design-rule enforcement. Schematics and layouts can be cross-probed to highlight instances and devices and identify unconnected nets quickly. The Virtuoso Layout Suite also introduces a new incremental connectivity-driven binding technology. This approach is far superior to traditional name-based schematic-to-layout binders, which had severe limitations when supporting schematic-to-layout name mismatches. The connectivity-driven binder enables better support of legacy layouts that have name mismatches, and also improves handling of engineering change orders (ECos) that involve renaming instances and terminals in the layout. The incremental nature of the FLExIBLE PCELLS Parameterized cells (Pcells) provide an advanced level of design automation to minimize tedious and repetitive layout tasks. Pcells support the changing of the size, shape, or contents of each cell instance without changing the original cell. They raise the level of abstraction to the component level. This dramatically improves the productivity of layout creation and editing of complex shapes and devices. Devices can be generated, edited, Figure 2: Docked layout assistants include a Design Navigator, Property Editor, and World View, which enhance layout productivity www. cadence. com VirTuoSo LAyouT SuiTE FAmiLy 3 connectivity binder also greatly improves the performance of a connectivity-driven layoutflow. COMMON CONSTRAINT SYSTEM The Virtuoso Layout Suite is built on the Virtuoso platform's common constraint system to greatly improve productivity. [. . . ] These types of custom routing can be fully automated in the Virtuoso Space-Based router environment and greatly improve layout designer productivity. The Virtuoso analog placer supports a number of analog/rF-centric automatic placement functions. This includes the automatic creation of quick placements and more robust placements that support FULL CUSTOM FLOORPLANNING TheVirtuosofloorplannercontains automaticandinteractivefloorplanning tools and technologies that help mixedsignal designers develop a layout from a schematic in a methodical manner. The floorplannersupportsI/Oconstraintsfiles, soft and hard rectilinear blocks, layout and abstract views, and digital/custom blocktypes. TheVirtuosofloorplanneris unique in its ability to add value to both top-down and bottom-up methodologies. Figure 5: The Virtuoso custom-digital placer automatically places transistors, devices, and cells in block- and cell-based designs using more traditional row-based techniques www. cadence. com VirTuoSo LAyouT SuiTE FAmiLy 5 more packing, as well as functions to fix DrC errors in the placement and adjust cell pins and sides. The Virtuoso analog placer offers three modes of operation: · Quickplacementmode, whichprovides fast, DrC-aware placement for quick area estimation · Quickplacementasschematicmode, which provides a placement-based device ordering in the schematic · Fullyautomatedplacement, which provides user-definable effort levels The Virtuoso custom-digital placer automatically places transistors, devices, and cells in block- and cell-based designs using more traditional row-based methods. [. . . ]