User manual DYNAMIC ENGINEERING PMC BISERIAL-II PS2
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Manual abstract: user guide DYNAMIC ENGINEERING PMC BISERIAL-II PS2
Detailed instructions for use are in the User's Guide.
[. . . ] DYNAMIC ENGINEERING
435 Park Dr. , Ben Lomond, Calif. 95005 831-336-8891 Fax 831-336-3840 sales@dyneng. com www. dyneng. com Est. 1988
User Manual
PMC BiSerial-II PS2
4 channel Bi-directional Serial Data Interface PMC Module
Revision A Corresponding Hardware: Revision A 10-2002-1201
PMC BiSerial-II PS2 Bi-Directional Serial Data Interface PMC Module
This document contains information of proprietary interest to Dynamic Engineering. It has been supplied in confidence and the recipient, by accepting this material, agrees that the subject matter will not be copied or reproduced, in whole or in part, nor its contents revealed in any manner or to any person except to meet the purpose for which it was delivered. [. . . ] The Direction and Termination register sets the direction of the bits. When the direction is set to output the bit definitions from this register are driven onto the corresponding parallel port lines. This port is direct read-write of the register. The IO side is read-back from the Status1 port also the lowest 8 bits. It is possible that the output data does not match the IO data in the case of the Direction bits being set to input.
Hardware and Software Design · Manufacturing Services Page 19
BIS2_STAT0
[$14] BiSerial II Status Port 0 read status, write clear STATUS 0 DATA BIT 31-25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DESCRIPTION Spare interrupt status f7_intr_lat f6_intr_lat f5_intr_lat f4_intr_lat f3_intr_lat f2_intr_lat f1_intr_lat f0_intr_lat r7_intr_lat r6_intr_lat r5_intr_lat r4_intr_lat r3_intr_lat r2_intr_lat r1_intr_lat r0_intr_lat rx3_intr_lat rx2_intr_lat rx1_intr_lat rx0_intr_lat tx3_intr_lat tx2_intr_lat tx1_intr_lat tx0_intr_lat
FIGURE 10
PMC BISERIAL-II STATUS REG 0 BIT MAP
When Interrupt Status is read as a one, it indicates that one or more latched interrupt conditions are true. In order for an actual system interrupt to occur, the interrupt enable for that condition and the Master Interrupt Enable must both be asserted. When this bit is zero, no interrupt conditions are pending.
Hardware and Software Design · Manufacturing Services Page 20
The interrupt conditions are latched and held in special interrupt status latches. The latched signals are made available on the Bis2_stat0 port. The latched bits remain set until the corresponding bit is written back to the port. When an interrupt occurs or if polling is used this port can be used to determine which channel requires attention. The active channel should be taken care of and then the bit set to clear the request. The combination of port access and bit position set is used to clear the bit. No second write is required to re-enable the latching mechanism. Tx0-3_intr_lat is set when the transmitter completes a transfer. To use as an interrupt the Tx_Int_En0-3 [Bis2_TX] must also be set as well as the master interrupt enable. Rx0-3_intr_lat is set when the receiver completes a reception. To use as an interrupt the Rx_Int_En0-3 [Bis2_RX] must also be set as well as the master interrupt enable. R0-7_intr_lat is set when the parallel port bit has received a rising transition 0->1. To use as an interrupt the par_int_en_r0-7 [Bis2_COSEN] must also be set as well as the master interrupt enable. F0-7_intr_lat is set when the parallel port bit has received a falling transition 1->0. To use as an interrupt the par_int_en_f0-7 [Bis2_COSEN] must also be set as well as the master interrupt enable.
Hardware and Software Design · Manufacturing Services Page 21
BIS2_STAT1
[$18] BiSerial II Status Port 1 read only FIFO Status, Parallel Data In & Switch Register DATA BIT 31-24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7-0 DESCRIPTION sw7-0 rx_fifo_full3 rx_fifo_full2 rx_fifo_full1 rx_fifo_full0 rx_fifo_mt3 rx_fifo_mt2 rx_fifo_mt1 rx_fifo_mt0 tx_fifo_full3 tx_fifo_full2 tx_fifo_full1 tx_fifo_full0 tx_fifo_mt3 tx_fifo_mt2 tx_fifo_mt1 tx_fifo_mt0 dat_in7-0
FIGURE 11
PMC BISERIAL-II STATUS 1 BIT MAP
The Switch Read Port has the user bits. The user bits are connected to the eight dip-switch positions. [. . . ] http://www. dyneng. com/warranty. html
Service Policy
Before returning a product for repair, verify as well as possible that the suspected unit is at fault. Then call the Customer Service Department for a RETURN MATERIAL AUTHORIZATION (RMA) number. Carefully package the unit, in the original shipping carton if this is available, and ship prepaid and insured with the RMA number clearly written on the outside of the package. Include a return address and the telephone number of a technical contact. [. . . ]
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