User manual ENHANCE SFX V2_2

[. . . ] SFX/SFX12V Power Supply Design Guide Version 2. 2 Document Revision Version Release Date 1. 0 1. 1 12/97 4/98 Notes Public release · · · Updated all mechanical outlines to clean up dimensioning of mounting holes. Added chassis cutouts for all mechanical outlines to clarify keep-out areas. Added Appendix C. Added SFX12V description Additional power ratings added Updated industry standards Increased standby current Section 4. 4 Updated Figure 4 SFX/SFX12V Connectors Section 5. 8 removed vendor name 2. 0 5/01 · · · · 2. 1 8/01 · · 2. 2 12/05 · · Section 3. 23 Typical Power Distribution. Change minimum loading on 5V rail to 0. 3A Section 3. 3. 2 PS_ON#. [. . . ] Capacitive Load The power supply should be able to power up and operate with the regulation limits defined in Table 2, Section 3. 2. 1 with the following capacitances simultaneously present on the DC outputs. Output Capacitive Loads Output +12 VDC +5 VDC +3. 3 VDC -12 VDC +5 VSB Capacitive load (µF) 5, 000 10, 000 6, 000 350 350 3. 2. 9. Closed-loop Stability The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive loads specified in Section 3. 2. 8. A minimum of 45 degrees phase margin and 10 dB gain margin is recommended at both the maximum and minimum loads. 3. 2. 10. +5 VDC / +3. 3 VDC Power Sequencing The +12 VDC and +5 VDC output levels must be equal to or greater than the +3. 3 VDC output at all times during power-up and normal operation. The time between the +12 VDC or +5 VDC output reaching its minimum in-regulation level and +3. 3 VDC reaching its minimum inregulation level must be 20 ms. 3. 2. 11. Voltage Hold-up Time The power supply should maintain output regulation per Section 3. 2. 1 despite a loss of input power at the low-end nominal range--115 VAC / 57 Hz or 230 VAC / 47 Hz--at maximum continuous output load as applicable for a minimum of 17 ms. Page 16 SFX/SFX12V Power Supply Design Guide Version 2. 2 3. 3. Timing / Housekeeping / Control Figure 2. Power Supply Timing Notes: T1 is defined in Section 3. 3. 4. T3, T4, T5, and T6 are defined in Table 12 3. 3. 1. PWR_OK PWR_OK is a "power good" signal. This signal should be asserted high by the power supply to indicate that the +12 VDC, +5 VDC, and +3. 3 VDC outputs are above the under voltage thresholds listed in Table 2 of Section 3. 2. 1 and that sufficient mains energy is stored by the converter to guarantee continuous power operation within specification for at least the duration specified in Section 3. 2. 11, "Voltage Hold-up Time. " Conversely, PWR_OK should be deasserted to a low state when any of the +12 VDC, +5 VDC, or +3. 3 VDC output voltages falls below its under voltage threshold, or when mains power has been removed for a time sufficiently long such that power supply operation cannot be guaranteed beyond the power-down warning time. The electrical and timing characteristics of the PWR_OK signal are given in Table 12 and in Figure 2. Page 17 SFX/SFX12V Power Supply Design Guide Version 2. 2 Table 12. PWR_OK Signal Characteristics Signal Type Logic level low Logic level high High-state output impedance PWR_OK delay PWR_OK rise time AC loss to PWR_OK hold-up time Power-down warning +5 V TTL compatible < 0. 4 V while sinking 4 mA Between 2. 4 V and 5 V output while sourcing 200 µA 1 k from output to common 100 ms < T3 < 500 ms T4 10 ms T5 16 ms T6 1 ms 3. 3. 2. PS_ON# PS_ON# is an active-low, TTL-compatible signal that allows a motherboard to remotely control the power supply in conjunction with features such as soft on/off, Wake on LAN, or wake-onmodem. When PS_ON# is pulled to TTL low, the power supply should turn on the four main DC output rails: +12 VDC, +5 VDC, +3. 3 VDC, and -12 VDC. When PS_ON# is pulled to TTL high or open-circuited, the DC output rails should not deliver current and should be held at zero potential with respect to ground. PS_ON# has no effect on the +5 VSB output, which is always enabled whenever the AC power is present. Table 13 lists PS_ON# signal characteristics. The power supply shall provide an internal pull-up to TTL high. The power supply shall also provide de-bounce circuitry on PS_ON# to prevent it from oscillating on/off at startup when activated by a mechanical switch. The DC output enable circuitry must be SELV-compliant. [. . . ] 51. 5 17. 1 9. 0 X 3. 2 cutout clearance under cutout minimum of 4. 5 from inside cover Airflow 115/220 No. 6-32 UNC-2B Threaded Hole (3X) 6. 0 31. 8 6. 0 88. 0 100. 0 Figure 7 Top Mount Fan Profile Mechanical Outline Page 35 SFX/SFX12V Power Supply Design Guide Version 2. 2 Ø4x3 59. 5 51. 5 4. 0 Note: all features of P/S enclosure that are outside bold cutout must be flush with wiht P/S face. Flush mount screws if necessary 8. 5 135° x 4 R5 25. 3 29. 8 34. 3 4. 0 14. 5 88. 0 96. 0 Figure 8 Chassis Cutout Fan recessed into top cover 17. 1 63. 5 Figure 9 Recessed Fan Mounting Page 36 SFX/SFX12V Power Supply Design Guide Version 2. 2 APPENDIX C PACKAGE C. 1 GUIDELINES FOR A REDUCED DEPTH, TOP MOUNT FAN OVERVIEW For applications requiring greater airflow directed 90° to the power supply top cover, such as a microATX or mini-tower chassis, with reduced depth, the power supply PCB could be repackaged in an enclosure with an 80 mm fan mounted to the top cover, with the length and depth dimensions rotated 90°. This provides greater flow of cooling air with better directed cooling. [. . . ]