User manual GIGABYTE GA-620

[. . . ] (on J13) Supports LDCM® Pentium® II Processor MAINBOARD REV. 1. 0 First Edition Release Date 98. 03. 19 2. 3. [. . . ] Quick Installation Guide : CPU SPEED SETUP The system bus speed is selectable between 66. 6MHz and 100 MHz. The user can select the system bus speed (JP6) and change the DIP SWITCH (SW) selection to set up the CPU speed for 200 - 633MHz processor. The CPU speed MUST match with the frequency RATIO. It will cause system hanging up if the frequency RATIO is higher than that of CPU. CLK RATIO SW 1 ON OFF ON OFF ON OFF SW 2 OFF OFF ON ON OFF OFF SW 3 ON ON OFF OFF OFF OFF SW 4 ON ON ON ON ON ON X3 X3. 5 X4 X4. 5 X5 X5. 5 JP6 1-2 CLOSE : 2-3 CLOSE : 1-2-3 OPEN : System Speed is set to 66 MHz Reserved (For Future use only!) System Speed is set to 100MHz 2 686BX I. Set system speed to 66MHz: JP6 pin 1-2 short will cause system always run at 66 MHz FSB (Front Side Bus). JP6 3 2 1 II. Set system speed to 100MHz: JP6 pin 1-2-3 open will cause system always run at 100MHz FSB. JP6 3 2 1 III. 82443BX 1 2 3 4 PIIX4 Function USB V0 USB D0USB D0+ GND USB V0 USB D1USB D1+ GND 5 6 7 JP6 8 J15: ATX Power Control Selection 82443BX PIIX4 JP6 J15 Open: Soft Off Close: Full On J13:Wake On LAN 13 Quick Installation Guide J13 82443BX PIIX4 JP6 1 Pin No. 1 J15 2 3 Function +5V SB GND Signal J14:Creative PCI Sound Card Support J14 82443BX PIIX4 SB-LINK 1 5 2 4 6 Pin No. 1 2 3 4 5 6 Function Signal GND NC Signal GND Signal JP6 14 686BX III. Top Performance Test Setting: The following performance data list is the testing results of some popular benchmark testing programs. Users have to modify the value for each item in chipset features as follow for top performance setting. ROM PCI / ISA BIOS CHIPSET FEATURES SETUP AWARD SOFTWARE, INC. EDO CASx# MA Wait State EDO RASx# Wait State SDRAM CAS latency Time DRAM Data Integrity Mode System BIOS Cacheable Video BIOS Cacheable Video RAM Cacheable 16 Bit I/O Recovery Time Memory Hole At 15M-16M Delayed Transaction Clock Spread Spectrum Slow Down CPU Duty Cycle Alarm When CPU Overheat CPU Temperature Select CPUFan Control *CPUFan Fail Alarm :1 :1 :2 : Non-ECC : Enabled : Enabled : Disabled :1 : Disabled : Disabled : Disable : Disable : Disabled : 75 ¢J/167 ¢K : Disabled : Disabled ESC : Quit F1 : Help F5 F6 F7 : Old Values Current CPU Temperature Current CPU FAN Speed Current CPUVCore A Current CPUVCore B Current +3. 3 V Current +5 V Current +12 V Current - 12 V Current - 5 V Current Battery Life : 56 ¢J /132 ¢K : 5152 RPM : 2. 83 V : 1. 50 V : 3. 53 V : 4. 99 V : 12. 28 V :-11. 81 V :-5. 04 V : OK ¡ôõ÷ö : Select Item ¡¡¡ PU/PD/+/(Shift)F2 : Modify : Color : Load BIOS Defaults : Load PERFORMANCE Defaults 15 Quick Installation Guide These data are just referred by users, and there is no responsibility for different testing data values gotten by users. [. . . ] EDO CASx# MA Wait State EDO RASx# Wait State SDRAM CAS latency Time DRAM Data Integrity Mode System BIOS Cacheable Video BIOS Cacheable Video RAM Cacheable 16 Bit I/O Recovery Time Memory Hole At 15M-16M Delayed Transaction Clock Spread Spectrum Slow Down CPU Duty Cycle Alarm When CPU Overheat CPU Temperature Select CPUFan Control *CPUFan Fail Alarm :1 :1 :2 : Non-ECC : Enabled : Enabled : Disabled :1 : Disabled : Disabled : Disable : Disable : Disabled : 75 ¢J/167 ¢K : Disabled : Disabled ESC : Quit F1 : Help F5 F6 F7 : Old Values Current CPU Temperature Current CPU FAN Speed Current CPUVCore A Current CPUVCore B Current +3. 3 V Current +5 V Current +12 V Current - 12 V Current - 5 V Current Battery Life : 56 ¢J /132 ¢K : 5152 RPM : 2. 83 V : 1. 50 V : 3. 53 V : 4. 99 V : 12. 28 V :-11. 81 V :-5. 04 V : OK ¡ôõ÷ö : Select Item ¡¡¡ PU/PD/+/(Shift)F2 : Modify : Color : Load BIOS Defaults : Load PERFORMANCE Defaults 15 Quick Installation Guide These data are just referred by users, and there is no responsibility for different testing data values gotten by users. (Different Hardware & Software configuration will result in different benchmark testing results. ) · CPU · DRAM · CACHE SIZE · DISPLAY · STORAGE · O. S. [. . . ]