User manual HP 9000 MODEL 725/50 WORKSTATION

[. . . ] These data sets have large numbers of small, complex components that are not always visible in the final images. For instance, when rendering an airplane, all of the MCAD parts are present in the data set represented by potentially millions of polygons that must be processed. However, when this airplane is viewed from the outside only the outer surfaces are visible, not the fan blades of the engine or the seats or bulkheads in the interior. In a traditional 3D z-buffered graphics system, all polygons in a scene must be processed by the graphics pipeline because it is not known a priori which polygons will be visible and which ones will be occluded (not visible). [. . . ] In either case the data is transmitted to and through all the texture and raster chips in the system. This path passes data directly through other pending operations. An example would be a texture cache download that is required to complete a primitive that is currently being rasterized, a situation that would lead to deadlock without the unbuffered path. 2D Path. This path runs directly through the interface chip to the texture and raster chips. The 2D path differs from the unbuffered path in the way its priority is handled. The interface chip manages priority among the three paths as they all converge on the same set of wires between the interface chip and the first texture chip. The unbuffered path goes directly through the interface chip to those wires and has priority over the other two paths. Data targeting the 2D path is held off until all preceding 3D work in the geometry chip has been flushed through to the first texture chip. the interface chip to the texture and raster chips. This provides a bypass method that allows traffic to get around Article 4 · © 1998 Hewlett Packard Company 30 May 1998 · The Hewlett-Packard Journal There is also special circuitry in the interface chip that is used to accelerate many operations commonly done by X11 or other 2D APIs. Buses The three primary buses in the system are each run at 200 MHz, allowing sustainable transfer rates of more than 800 Mbytes per second. To control the loading on the interconnections for these buses, they are built as point-to-point connections from one chip to the next. Each chip receives the signals and then retransmits them to the next chip in the sequence. These operations include: H Transformation of the coordinates from model space to eye space H Computing a vertex color based on the lighting state, which consists of up to eight directional or positional light sources H Texture map calculations that include: V V V V Environment map calculations for texture mapping Texture coordinate transformation Linear texture coordinate generation Texture projection H View volume clipping and clipping against six arbitrary application-specified planes to determine whether a primitive is completely visible, rejected because it is completely outside the view area, or needs to be reduced into its visible components H Perspective projection transformation to cause primitives to look smaller the further away from the eye they are H Setup calculations for rasterization in the raster chip. There were some interesting problems to solve in the design of the distribution and coalescing of work up and down the geometry chip daisy chain. For example, load balancing, maintaining strict order in the output stream, and ensuring that operations, such as binding of colors and normals to vertices, perform as required by OpenGL. Article 4 · © 1998 Hewlett Packard Company 31 May 1998 · The Hewlett-Packard Journal Fast Virtual Texturing Texture mapping, which is wrapping a picture over a three dimensional object, has been used over the years as a key feature to enhance photorealism, reduce data set sizes, perform visual analysis, and aid in simulations (see Figure 1). Since texturing calculations are computationally expensive and memory access for large textures can be prohibitively slow, various workstation graphics vendors have provided hardware-accelerated texture mapping as a key differentiator for their product. A primary drawback of these attempts at hardware acceleration is that dedicated local hardware texture memory is limited Figure 1 in size and is expensive. To take advantage of the performance boost, graphics applications were constrained to textures that fit in the local hardware texture memory. In other words, the application was responsible for managing this hardware resource. Noticing this obvious artificial application limitation in texturing functionality, performance, and portability, Hewlett-Packard introduced, in the VISUALIZE-48, a new concept in hardware texture mapping called virtual texture mapping. Virtual texture mapping uses the dedicated local hardware texture memory as a true texture cache, swapping in and out of the cache the portions of textures that are needed for rendering a 3D image. Thus, for texturing applications, these limitations were eliminated. The application could define and use a texture map of any size (up to a theoretical limit of 32K texels × 32K texels*) that would be hardware accelerated, eliminating the need for the application to be responsible for managing local texture memory. Using the local hardware texture memory as a cache also means that this memory uses only the portions of the texture maps needed to render the image. [. . . ] Scott Noel Scott is a senior engineer at the HP Workstation Systems Division. He is responsible for product definition, performance projections, and modeling. He designed the I/O bus for the geometry chip described in the article. He came to HP in 1981 after receiving a BS degree in computer engineering from the University of Kansas. Daniel M. [. . . ]