User manual INTEL 2ND GENERATION INTEL CORE PROCESSOR FAMILY DESKTOP DATASHEET VOLUME 1 01-2011

[. . . ] 2nd Generation Intel® CoreTM Processor Family Desktop Datasheet, Volume 1 Supporting Intel® CoreTM i7, i5 and i3 Desktop Processor Series This is Volume 1 of 2 January 2011 Document Number: 324641-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Legal Lines and Disclaimers UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. [. . . ] The 32-bit logical x2APIC ID is partitioned into two sub-fields--a 16-bit cluster ID and a 16-bit logical ID within the cluster. Consequently, ((2^20) -16) processors can be addressed in logical destination mode. Processor implementations can support fewer than 16 bits in the cluster ID sub-field and logical ID sub-field in a software agnostic fashion. · More efficient MSR interface to access APIC registers -- To enhance inter-processor and self directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR based interfaces in the x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in the x2APIC mode. · The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the Interrupt Command Register (ICR) and End Of Interrupt (EOI) registers have been modified to allow for more efficient delivery and dispatching of interrupts. Datasheet, Volume 1 41 Technologies The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the "x2APIC" mode. To benefit from x2APIC capabilities, a new Operating System and a new BIOS are both needed, with special support for the x2APIC mode. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendibility for future Intel platform innovations. Note: Intel x2APIC technology may not be available on all processor SKUs. For more information, refer to the Intel® 64 Architecture x2APIC Specification at http://www. intel. com/products/processor/manuals/ §§ 42 Datasheet, Volume 1 Power Management 4 Power Management This chapter provides information on the following power management topics: · ACPI States · Processor Core · Integrated Memory Controller (IMC) · PCI Express* · Direct Media Interface (DMI) · Processor Graphics Controller 4. 1 4. 1. 1 Table 4-1. ACPI States Supported The ACPI states supported by the processor are described in this section. System States System States State G0/S0 G1/S3-Cold G1/S4 G2/S5 G3 Full On Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). Description 4. 1. 2 Table 4-2. Processor Core/Package Idle States Processor Core/Package State Support State C0 C1 C1E C3 C6 Active mode, processor executing code. AutoHALT state with lowest frequency and voltage operating point. Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to the L3 shared cache. Execution cores in this state save their architectural state before removing core voltage. Description Datasheet, Volume 1 43 Power Management 4. 1. 3 Table 4-3. Integrated Memory Controller States Integrated Memory Controller States State Power up Pre-charge Power-down Active PowerDown Self-Refresh CKE asserted. CKE de-asserted (not self-refresh) with all banks closed. CKE de-asserted (not self-refresh) with minimum one bank active. CKE de-asserted using device self-refresh. Description 4. 1. 4 Table 4-4. PCIe Link States PCIe Link States State L0 L0s L1 L3 Full on ­ Active transfer state. First Active Power Management low power state ­ Low exit latency. [. . . ] The set of DC electrical specifications shown in Table 7-11 is used with devices normally operating from a VCCIO interface supply. VCCIO nominal levels will vary between processor families. All PECI devices will operate at the VCCIO level determined by the processor installed in the system. For specific nominal VCCIO levels, refer to Table 7-6. Table 7-11. [. . . ]