User manual INTEL 6 SERIES CHIPSET DATASHEET 01-2011

[. . . ] Intel® 6 Series Chipset Datasheet January 2011 Document Number: 324645-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY O0R DEATH MAY OCCUR. [. . . ] Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the Gigabit LAN device. This bit controls access to the I/O space registers. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the Gigabit LAN device. Attribute: Size: Description R/W, RO 16 bits 7 5 4 3 Datasheet 435 Gigabit LAN Configuration Registers 12. 1. 4 PCISTS--PCI Status Register (Gigabit LAN--D25:F0) Address Offset: 06h­07h Default Value: 0010h Bit Attribute: Size: Description R/WC, RO 16 bits Detected Parity Error (DPE) -- R/WC. 1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity error. This is set even if PCIMD. PER (D25:F0, bit 6) is not set. 1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic. 13 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Set when the GbE LAN controller receives a completion with unsupported request status from the backbone. 12 0 = Root port has not received a completion with completer abort from the backbone. 1 = Set when the Gb LAN controller receives a completion with completer abort from the backbone. 1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream device onto the backbone. Master Data Parity Error Detected (DPED) -- R/WC. 1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbone and PCIMD. PER (D25:F0, bit 6) is set. Fast Back to Back Capable (FB2BC) -- RO. Indicates the presence of a capabilities list. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. If MSI is not enabled, this bit is set regardless of the state of PCICMD. Interrupt Disable bit (D25:F0:04h:bit 10). 2:0 Reserved 10:9 7 6 5 4 436 Datasheet Gigabit LAN Configuration Registers 12. 1. 5 RID--Revision Identification Register (Gigabit LAN--D25:F0) Offset Address: 08h Default Value: See bit description Bit 7:0 Revision ID -- RO. Intel® Attribute: Size: Description RO 8 bits 6 Series Chipset Specification Update for the value 12. 1. 6 CC--Class Code Register (Gigabit LAN--D25:F0) Address Offset: 09h­0Bh Default Value: 020000h Bit 23:0 020000h = Ethernet Adapter. Attribute: Size: Description RO 24 bits Class Code-- RO. Identifies the device as an Ethernet Adapter. 12. 1. 7 CLS--Cache Line Size Register (Gigabit LAN--D25:F0) Address Offset: 0Ch Default Value: 00h Bit 7:0 Attribute: Size: Description R/W 8 bits Cache Line Size -- R/W. [. . . ] This bit is connected by HW to bit 5 (THRE) of this register. Transmit Holding Register Empty (THRE)-- RO. This bit is always set when the mode (FIFO/Non-FIFO) is changed by the Host. This bit is active only when the THR operation is enabled by the FW. [. . . ]