User manual INTEL 852GM DESIGN GUIDE

[. . . ] R Intel® 852GM Chipset Platform Design Guide For Use with the Mobile Intel® Pentium® 4 Processor-M, Mobile Intel® Celeron® Processor on . 13 Micron Process in the 478-Pin Package, and Intel® Celeron® M Processor January 2005 Document Number: 252338-003 R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. [. . . ] Because many variables within a mobile system can affect the temperature measured at any given point in a system, the expected usage and effectiveness of ETS# is also very focused. Because of factors such as thermal sensor placement, airflow within a mobile chassis, adjacent components, thermal sensor sensitivity, and thermal sensor response time, ETS# can effectively be used for controlling skin temperatures. However, ETS# should not be used for measuring or controlling the Tj or Tcase parameters of DDR-SDRAM devices since due to the location of the thermal sensor it cannot respond quickly enough to dynamic changes in DRAM power. 7. 7. 2. ETS# Design Guidelines ETS#, as implemented in the GMCH, is an active low signal and does not have an integrated pull-up to maintain a logic 1. As a result of this, a placeholder for an external 8. 2 k to 10 k pull-up resistor should be provided near the ETS# pin. Electrical details on output characteristics of suitable thermal sensors for use with the GMCH are currently not finalized. The currently recommended pull-up voltage for this external pull-up should be 3. 3 V. The thermal sensor should implement an open drain type output buffer to drive ETS#. A system is expected to have one thermal sensor per SO-DIMM connector on the motherboard. As a result, routing guidelines for the output of these thermal sensors to the ETS# pin will also be important. 126 Intel® 852GM Chipset Platform Design Guide System Memory Design Guidelines (DDR-SDRAM) R 7. 7. 3. Thermal Sensor Placement Guidelines The many factors that can affect the accuracy of ambient temperature measurements by thermal sensors make the placement of them a very critical and especially challenging task. Ideally, one thermal sensor should be placed near each SO-DIMM in a system. The thermal sensor should be located in an area where the effects of airflow and effects of conduction from adjacent components are minimized. This allows for the best correlation of thermal sensor temperature to chassis or notebook surface temperature. Assuming airflow is negligible within a system, the optimal placement of the thermal sensor is on the surface of the motherboard directly beneath the shadow of an SO-DIMM module centered longitudinally and laterally in relation to the outline of the SO-DIMM. The thermal sensor should have a form factor small enough to allow it to fit beneath double-sided memory modules (i. e. modules with memory devices on both sides of a module). If placement within the outline of an SO-DIMM is not possible, then the next best option is to locate it within approximately 15 mm (0. 6 inches) of the outline/SO-DIMM shadow. Again, this assumes negligible effects from airflow. Figure 62. DDR Memory Thermal Sensor Placement 15mm 15mm Hashed Area: Recommended area for DRAM ETS# sensor on motherboard. Best Location is sensor under S0-DIMM. May not be mechanically feasible in all designs due to small gap between SO-DIMM and motherboard. Top View ­ SO-DIMM Side View ­ SO-DIMM Sensor location within approx 15mm of SO-DIMM outline will be not be as effective at controlling fast transient temperature changes Intel® 852GM Chipset Platform Design Guide 127 System Memory Design Guidelines (DDR-SDRAM) R This page intentionally left blank. 128 Intel® 852GM Chipset Platform Design Guide Integrated Graphics Display Port R 8. Integrated Graphics Display Port The GMCH contains four display ports: an analog CRT port, a dedicated LVDS port, and one 12-bit Digital Video Out (DVO) port. Section 8. 1 will discuss the CRT and RAMDAC routing requirements. Section 8. 2 will discuss the dedicated LVDS port. Section 8. 3 will discuss DVOC design guideline. [. . . ] The 2 parts will be arranged as shown on this schematic page. 22, 23 -V12S C8A2 22UF 35V 16, 21, 39, 40 +VDC 15, 17, 23, 27, 37 +V12S C2B1 22UF 35V 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 38. . 40, 42, 47 5, 6, 8, 9, 11, 15, 16, 18, 20, 21, 23, 26, 31, 33. . 36, 38. . 40, 42, 48 +V3. 3S +V5S C7E7 22UF R6J5 10K SW7J1 1 3 4 1 2 Push button RST_PUSH# 2 U6J1 GND IN VCC OUT 4 22UF 3 MASTER_RESET# 4 4 CON3, RCPTL, TH, 700000-667. Normal J1B2 A1 A2 A3 A4 9, 15, 19, 20, 47, 48 D1 D2 D3 D4 F1 F2 F3 F4 3Pin_RECEPTICLE 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 38. . 40, 42, 47 +V5S_TURNER R1D1 0. 01_1% 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 38. . 40, 42, 47 15, 17, 23, 27, 37 +V12S +V12S_TURNER R1C4 0. 01_1% R6J2 330 +V2. 5_TURNER +V5S 3 RST_PUSH#_D +V5S +V1. 5S C6J3 0. 1UF 20. . 23, 27, 36, 37, 42, 43 +V5 C1E1 , 33. . 36, 38. . 40, 42, 48 +V3. 3S R1C1 +V3. 3S_TURNER C1C1 22UF 0. 002_1% RESET 1 CR6J2 BAT54 MAX6816 3 3 CON3, RCPTL, TH, 700000-667. Normal J1C1 32, 37 AC_PRESENT# 37, 48 GATED_SMC_SHUTDOWN 32, 37 SMC_ONOFF# 32, 36, 37 SMB_SB_CLK 32, 36, 37 SMB_SB_DATA 32, 36, 37 SMB_SB_ALRT# 19, 20, 32, 37, 38, 43 PM_SLP_S4# 19, 25, 32, 37, 38, 43 PM_SLP_S3# 6, 19, 37, 38 PM_SLP_S1# 39 PWR_PWROK , 23 -V12S -V12S_TURNER R1C3 8 2 PS_ON_SW# 0. 01_1% R1D2 +V3. 3A_TURNER +V3. 3ALWAYS 0. 002_1% C1D1 22UF A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 J1D1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 8, 15. . 18, 20, 23. . 25, 27, 34, 35, 38. . 40, 42, 47 +V5S +V5 J6J1 FRONT1 1 3 5 7 9 11 13 15 20. . 23, 27, 36, 37, 42, 43 FRONT2 SW3_CONN_D 3 CR6J1 BAT54 1 C6J7 470PF R6J4 330 POWER SW8J1 3 1 4 2 Push button 72Pin_RECEPTICLE(male) 26, 27 IDE_PDACTIVE# C6J4 C6J6 C6J8 2 4 6 8 10 12 16 C6J5 470PF PS_ON_SW# 470PF 470PF 470PF HDR_2x8 2 1. 5V_EV 47 5, 15, 19. . 23, 27. . 29, 32, 36. . 39, 48 +V3. 3ALWAYS 5 U1E2 4 PM_SYSRST# 19 C1E5 0. 1UF Front Panel Connector MASTER_RESET# 3, 5, 47 ITP_DBRESET# 1 2 74AHC1G08 CON72, RCPTL, TH, 700000-668. Normal A1 A2 A3 A4 1 20. . 23, 27, 36, 37, 42, 43 D1 D2 D3 D4 +V5_TURNER R1D3 +V5 0. 01_1% 3 1 , 35, 37. . 39, 43 +V3. 3 +V3. 3_TURNER R1D4 0. 01_1% F1 F2 F3 F4 3Pin_RECEPTICLE Title Size A C DC/DC Connector Project: Intel 852GM CRB D CON3, RCPTL, TH, 700000-667. Normal A B Document Number A# 44 of E Rev 59 A B C D E Power On Sequence +VDC 4 5 5 5 5 5 5 5 5 DC/DC PM_SLP_S4# PM_SLP_S3# 18 4 4 PCI_RST# 4 +V1. 5S +V3. 3 +V3. 3S +V5S +V5 +V12S -V12S ICH4 PG 19 18 DELAYED_VR_PWRGD GMCH PG 7 H_PWRGD H_CPURST# POWER 1 PS_ON_SW# PM_PWRBTN# PG 41 PWR_PWROK 6 V1. 5_PWRGD U7A3 PG 39 DDR_VR_PWRGD 7 MAIN_PWROK MAIN2_PWROK U7A6 PG 39 8 PM_PWROK PM_RSMRST# 17 PG 44 3 U7B1 3 V5A_PWRGD 2 +V3A 3 PG 38 19 3 PG 39 CPU PG 3 PG 20 +V1. 5A SMC SMC_ONOFF# PG 32 VR_PWRGD_CK408# IMVP_PWRGD DDR VR PG 43 2 +V3A +V2. 5 +V1. 25S SMC_PROG_RST# 2 SMC_RST# 9 VR_ON 16 CK-408 PG 6 MAX809 PG 33 +V5A VR PG 21 +V5_ALWAYS U8A2 PG 29 RST_HDR 2 PG 39 VR_SHUTDOWN ON_BOARD_VR_ON U4B5 PG 39 U4B4 10 INTERPOSER_PRES# VR_ON GMCH_VCORE_PWRGD Core VR PG 40 12 1 11 MGM & VCCP VR PG 42 10 13 ON_BOARD_VR_PWRGD U4B3A U4B3B PG 36 14 U7A5 PG 36 Title Size A 15 1 INTERPOSER_PRES OFF_BOARD_VR_PWRGD U4B3D PG 36 Power On Check list Project: Intel 852GM CRB D Document Number A# of 45 E Rev 59 A B C A B C D E PS_ON_SW# SW7J1 PG 44 Reset Map PCI_RST# BUF_PCI_RST# DC/DC Turner 4 SMC_SHUTDOWN PWR_PWROK PG 44 SW6 PCI SLOTS PG22 4 U7A3 PG 39 PM_PWROK ICH4 PG 18 PM_RSMRST# MASTER_RESET# PG 40 Core VR PG 39 3 Q9B3 PG32 PCI_GATED_RST# R=0 R=0 DOCKING ITP PG 5 U7A4 PG 33 SMC PG 22 LPC SLOT PG 37 3 ADD SLOT PG 15 2 MAX809 PG 33 SMC_PROG_RST# SMC_RST# U8A2 PG 32 SMC_RES# 2 PG 32 FWH PG 31 H_CPURST# MCH H_PWRGD SIO PG 34 CPU PG 7 1 PG 3 Title Size A A B C 1 Reset Map Project: Intel 852GM CRB D Document Number A# 46 of E Rev 59 A B C D E INTEL(R) CELERON(R) M PROCESSOR / INTEL(R) 852GM CHIPSET CUSTOMER REFERENCE BOARD 4 Fab 4 REV 4. 403 4 Fan Header PG 38 CPU Thermal Sensor PG 5 INTEL(R) CELERON(R) M PROCESSOR 478 uFCPGA PG 3, 4 ITP PG 5 CK-408 Clocking PG 6 SS Clocking PG 6 Test Points PG 37 852GM VR PG 43 IMVP-IV VR PG 39, 40, 41 PSB PG 13 PG 11 PG 13 PG 12 SODIMM0 ADD Card Connector PG 15 3 DVO Bus Backlight Connector PG 16 LVDS PG 16 Intel(R ) 852GM chipset 732 uFCBGA PG 7, 8, 9, 10 DDR SDRAM 200/266 MHz SODIMM1 PG 14 3 PG 46 DAC (CRT) PG 17 EVMC SLOT DDR VR PG 44 PG 22 PG 22 PG 23 5V PCI SLOT 1 5V PCI SLOT 2 IDE0 IDE1 ATA 100 33MHz PCI PG 29 USB5 (Docking) PG 29 USB2 PG 29 USB4 ICH4-M USB 2. 0 421 BGA PG 18, 19, 20, 21 AC97 LAN CONNECT 5V PCI SLOT 3 PG 24 PG 25 PG 28 USB0 PG 28 USB1 PG 28 USB3 82562EM PG 30 2 2 MDC Header PG 27 RJ45 Docking Connector PG 26, 27 Hub Interface 66MHz PG 10 Q-Switch PG 37 LPC, 33MHz Turner System DC/DC Connector PG 45 FWH On Board VR 1. 5V Always, 5V Always 1. 5V PG 21 Serial Parallel PG 35 8 Mbit PG 31 SIO PC87393 PG 34 PORT 80--83 Suspend Timer SMC/KBC Hitachi H8S 2149 PS/2 PG 36 LPC PM Headers PG 33 PG 32 PS/2 PG 36 PG 33 FIR PG 35 FDD PG 35 Scan KB PG 37 1 PG 35 PG 36 LPC SLOT 1 Title Block Diagram Document Number C26116 1 of Sheet E Size Project: Intel Celeron M / 852GM CRB A Wednesday, January 12, 2005 Date: A B C D Rev 4. 403 51 A B C D E CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION Voltage Rails 4 I C / SMB Addresses Primary DC system power supply (10 to 21V) Core voltage for processor 1. 05V rail for processor PSB, 852GM PSB 1. 8V for processor PLL and VID circuitry 1. 25V DDR Termination voltage 1. 35V for 852GM core 1. 5V switched power rail (off in S3-S5) 1. 5V always on power rail 1. 5V power rail (off in S4-S5) 2. 5V power rail for DDR 3. 3V always on power rail 3. 3V power rail (off in S4-S5) 3. 3V switched power rail (off in S3-S5) 5. 0V for ICH4M's VCC5REFSUS 5. 0V power rail (off in S4-S5) 5. 0V switched power rail (off in S3-S5) 12. 0V switched power rail (off in S3-S5) -12. 0V switched power rail for PCI (off in S3-S5) Device Clock Generator Spread Spectrum Clock SO-DIMM0 SO-DIMM1 Thermal Sensor Header LVDS Backlight Inverter Dock Connector Smart Battery Smart Battery Charger Smart Selector Bluetooth Header LPC Pwr Mngmnt Header LPC Pwr Mngmnt Header Thermal Diode EV Support: DV0-DV3 V5-V8 PV0-PV3 DV4 V9-V12 I1-I4 EP1-EP4 PV4 V1-V4 Address 1101 001x 1101 010x 1010 000x 1010 001x 1001 000x ____ ____ ____ ____ 0001 011x 0001 001x 0001 010x ____ ____ ____ ____ ____ ____ 1001 110x 0101 0001 0101 0010 0101 0011 0101 0100 0101 0101 0101 0110 0101 0111 0101 0100 0101 1001 Hex D2 D4 A0 A2 90 __ __ 16 12 14 __ __ __ 9C 51 52 53 54 55 56 57 58 59 Bus SMB_ICH_S SMB_ICH_S SMB_ICH_S SMB_ICH_S SMB_ICH SMB_ICH SMB_ICH SMB_SB SMB_SB SMB_SB SMB_SB SMB_SB SMB_THRM SMB_THRM SMB_ICH SMB_ICH SMB_ICH SMB_ICH SMB_ICH SMB_ICH SMB_ICH SMB_ICH SMB_ICH 2 Default Jumper Settings 4 3 +VDC +VCC_CORE +VCCP +V1. 8S +V1. 25S +V1. 35S +V1. 5S +V1. 5ALWAYS +V1. 5 +V2. 5 +V3. 3ALWAYS +V3. 3 +V3. 3S +V5ALWAYS +V5 +V5S +V12S -V12S Jumper J3F3 J7B2 J7B3 J7B4 J7B5 J7C1 J6E1 J6D1 J4F1 J2J3 J8J2 J9E2 J9E4 J9E5 J9B1 J8A2 J9A1 J9A3 J8A1 J9H1 J9G2 J3G1 J1H4 J1H5 J9J2 Default 1-X 1-X 1-2 1-2 1-2 1-2 2-3 1-X 1-X 1-X 2-3 1-2 1-2 2-3 1-X 1-2 1-X 1-X 1-2 1-X 1-2 1-X 1-X 1-X 1-X Option 1-2 1-2 1-X 1-X 1-X 1-X 1-2 1-2 1-2 1-2 1-2 2-3 2-3 1-2 1-2 2-3 1-2 1-2 1-X 1-2 2-3 1-2 1-2 1-2 1-2 Description CPU BSEL Override GMCH Strap: PSB Voltage GMCH Strap: DVO Strap GMCH Strap: Clock Config GMCH Strap: Clock Config GMCH Strap: Clock Config LVDS EV No-Shunt Default No-Shunt Default CMOS Clear CRB/SV Detect Moon ISA Support Moon ISA Support Moon ISA Support SMC/KBC Programming SMC/KBC Disable KBC 60/64 Decode Disable SMC_LID Disable NMI Jumper Port 80-81/82-83 Select SIO Disable DDR EV Support A_FAN_P1 A_FAN_P0 EVMC ITP_DBRESET# Page 03 08 08 08 08 08 08 09 09 19 19 23 23 23 32 32 32 32 33 33 34 44 46 46 46 3 PCI Devices Device Slot 1 Slot 2 Slot 3 Docking LAN IDSEL # AD16 AD17 AD18 AD28 (AD24 internal) REQ/GNT # 1 1 2 2 3 3 4 4 Interrupts F, G, H, E G, F, E, H C, D, B, A (E, F, G, H optional) B, C, D, A A, B PC/PCI A A A B LEDs and Switches LED Primary IDE Secondary IDE SMC/KBC Num Lock SMC/KBC Scroll Lock SMC/KBC Caps Lock VID0 VID1 VID2 VID3 VID4 VID5 S0 State S1 State S3 State S4 State S5 State Switch Virtual Battery On/Off Lid Power On/Off Reset Page 27 27 32 32 32 34 34 34 34 34 34 38 38 38 38 38 Page 32 32 45 45 Reference DS2J2 DS2J1 DS8A1 DS8A2 DS8B1 DS1J1 DS1J2 DS1J3 DS1J4 DS2J3 DS2J4 DS1H1 DS1H3 DS1H2 DS2H2 DS2H1 Reference SW8A1 SW9A1 SW8J1 SW7J1 Wake Events RI# (Ring Indicate) from serial port PME# (Power Management Event) from PCI/mini-PCI slots, ADD slot, LPC slot LAN I/O from 82562EM LID switch attached to SMC USB AC97 wake on ring SmLink for AOL II Hot Key from the scan matrix keyboard 2 Net Naming Conventions Suffix # = Active Low Signal Prefix H = Host M = DDR Memory TP = Test Point (does not connect anywhere else) 2 PCB Footprints SOT-23 3 2 As seen from top 1 1 2 3 5 SOT23-5 Power States SIGNAL STATE Full ON S1M (Power On Suspend) 1 4 SLP_S1# HIGH LOW LOW LOW LOW SLP_S3# HIGH HIGH LOW LOW LOW SLP_S4# HIGH HIGH HIGH LOW LOW SLP_S5# +V*ALWAYS HIGH HIGH HIGH HIGH LOW ON ON ON ON ON +V* ON ON ON OFF OFF +V*S ON ON OFF OFF OFF Clocks ON LOW OFF OFF OFF Stuff / No_Stuff Resistors for Celeron M A0 / A1 Resistor R3T1 R2T3 CeleronM A0 Stuffed Stuffed Celeron M A1 and follow-on silicon No_Stuffed No_Stuffed 1 S3 (Suspend to RAM) S4 (Suspend To Disk) S5 / Soft OFF Title Size A Date: C Notes and Annotations Project: Intel Celeron M / 852GM CRB Wednesday, January 12, 2005 D Document Number C26116 Sheet 2 of E Rev 4. 403 51 A B A B C D E 8 H_A#[31:3] U2E1A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 U3 R2 P3 T2 P1 T1 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5 C2 D3 A3 C6 D1 D4 B4 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0 ADS# BNR# BPRI# DEFER# DRDY# DBSY# N2 L1 J3 L4 H2 M2 N4 A4 B5 J2 B11 H1 K1 L2 M3 K3 K4 C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7 B17 B18 A18 C17 A15 A16 B14 B15 H_PROCHOT# H_IERR# H_INIT# 18, 37 H_ADS# H_BNR# H_BPRI# 8 8 8 +VCCP 4, 5, 9, 18. . 20, 40, 42, 43, 46 ADDR GROUP 0 H_DEFER# 8 H_DRDY# 8 H_DBSY# 8 H_BR0# 8 R2E1 56 4 CONTROL 4 BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM# BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# 8 8 H_ADSTB#0 H_REQ#[4:0] H_LOCK# 8 H_CPURST# 5, 8 H_RS#0 8 H_RS#1 8 H_RS#2 8 H_TRDY# 8 H_HIT# H_HITM# 8 8 Place testpoint on H_IERR# with a GND 0. 1" away REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1 8 H_D#[63:0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 C23 C22 D25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 K24 L24 J26 U2E1B D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF3 GTLREF2 GTLREF1 GTLREF0 D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 W25 W24 T24 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 AE24 AE25 AD20 P25 P26 AB2 AB1 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#[63:0] 8 8 H_A#[31:3] ITP SIGNALS TDI_FLEX 5 H_TDO 5 H_TMS 5 H_TRST# 5 ITP_DBRESET# 5, 45, 46 R3E1 56 H_THERMDA 5 H_THERMDC 5 PM_THRMTRIP# 19 CLK_ITP_CPU# 6 CLK_ITP_CPU 6 CLK_CPU_BCLK# 6 CLK_CPU_BCLK 6 +VCCP 4, 5, 9, 18. . 20, 40, 42, 43, 46 3 DATA GRP 0 H_BPM0_ITP# 5 H_BPM1_ITP# 5 H_BPM2_ITP# 5 H_BPM3_ITP# 5 H_BPM4_PRDY# 5 H_BPM5_PREQ# 5 H_TCK 5 +VCCP 4, 5, 9, 18. . 20, 40, 42, 43, 46 H_TDI pullup (R3T3) must be placed within 300ps of CPU TDI pin (within 2") R3T3 150 ADDR GROUP 1 DATA GRP 2 3 18 18 18 18, 37 18, 37 18, 37 18, 37 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# Processor-Skt THERM 8 H_ADSTB#1 PROCHOT# THERMDA THERMDC 8 8 8 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 8 8 8 H_DSTBN#1 H_DSTBP#1 H_DINV#1 H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8 Comp0 Comp1 Comp2 Comp3 +VCCP 4, 5, 9, 18. . 20, 40, 42, 43, 46 R2T1 330 THERMTRIP# ITP_CLK1 ITP_CLK0 BCLK1 BCLK0 H CLK 4, 5, 9, 18. . 20, 40, 42, 43, 46 2 +VCCP DATA GRP 1 DATA GRP 3 2 5, 6, 8, 9, 11, 15. . 18, 20, 21, 23, 26, 31, 33. . 36, 38. . 40, 43, 45, 51 +V3. 3S R4D2 1K_1% R4F5 1. 3K 5% CPU_BSEL0_DQ Layout note: COMP0 and COMP2 need to be Zo=27. 4ohm traces. Best estimate is 18mil wide trace for outer layers and 14mil if on internal layer. See DG of Processor. Traces should be shorter than 0. 5". Refer to latest CS layout COMP1, COMP3 should be routed as Zo=55ohm traces shorter than 0. 5" R4F4 330 H_GTLREF 46 0. 5" max length TP_GTLREF3 AC1 TP_GTLREF2 G1 TP_GTLREF1 E26 AD26 A1 B2 6, 8 CK408_SEL1 CR4F1B 3904 6 2 1 R3D1 2K_1% MISC NC0 NC1 TP_B_SEL1 C14 RSVD1 TP_NC_2 C3 RSVD2 TP_NC_3 J3F3 AF7 CPU_BSEL0_J C16 RSVD3 1 2 RSVD4 E1 PSI# PM_PSI# 39, 40 Processor-Skt J3F3 should open to support Celeron M DPSLP# DPWR# PWRGOOD SLP# TEST1 TEST2 B7 C19 E4 A6 C5 F23 TEST1 TEST2 H_DPSLP# 7, 18, 37 H_DPWR# 7 H_PWRGD 18, 37 H_CPUSLP# 18, 37 3 CR4F1A 3904 5 4 CPU_BSEL0_D R4F2 330 CPU_BSEL0 Comp0 Comp1 Comp2 Comp3 1 R3T1 NO_STUFF_1K R3T1 & R2T3 are to be stuffed for A0 silicon and no_stuffed for A1 and follow-on silicon R2T3 NO_STUFF_1K 1 R4F3 1K R2R1 54. 9_1% R2R2 27. 4_1% R3R2 54. 9_1% R3R3 27. 4_1% Title Intel Celeron M Processor 1 of 2 Document Number C26116 of 3 Sheet E Project: Size Intel Celeron M / 852GM CRB Custom Wednesday, January 12, 2005 Date: A B C D Rev 4. 403 51 A B C One 0. 01uF & 10uF cap for each VCCA pin. [. . . ]