User manual INTEL ATOM PROCESSOR N 500 SPECIFICATION UPDATE REVISION 001

[. . . ] Intel® AtomTM Processor N500 Series Specification Update September 2010 Revision 001 Document Number: 324341-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. [. . . ] Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used. Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Status: For the steppings affected, see the Summary Tables of Changes. BH8 Problem: Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32-bit mode. Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected but the memory state may be only partially saved or restored. Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and 32-bit mode memory limits. Status: For the steppings affected, see the Summary Tables of Changes. BH9 Problem: A Thermal Interrupt is Not Generated when the Current Temperature is Invalid When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9, 7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is crossed. Status: For the steppings affected, see the Summary Tables of Changes. Specification Update 17 Errata BH10 Problem: Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unexpected Thermal Interrupts Software can enable DTS thermal interrupts by programming the thermal threshold and setting the respective thermal interrupt enable bit. When programming DTS value, the previous DTS threshold may be crossed. This will generate an unexpected thermal interrupt. Implication: Software may observe an unexpected thermal interrupt occur after reprogramming the thermal threshold. Workaround: In the ACPI/OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value. Status: For the steppings affected, see the Summary Tables of Changes. BH11 Problem: Returning to Real Mode from SMM with EFLAGS. VM Set May Result in Unpredictable System Behavior Returning back from SMM mode into real mode while EFLAGS. VM is set in SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the value of the EFLAGS. VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround: SMM software should not change the value of EFLAGS. VM in SMRAM. Status: For the steppings affected, see the Summary Tables of Changes. BH12 Problem: Fault on ENTER Instruction May Result in Unexpected Value on Stack Frame The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected value (i. e. residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer to "Procedure Calls For Block-Structured Languages" in IA-32 Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when transferring to ring 0. Intel has not observed this erratum on any commercially available software. Status: For the steppings affected, see the Summary Tables of Changes. 18 Specification Update Errata BH13 With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap before Retirement of Instruction If an FP instruction generates an unmasked exception with the EFLAGS. TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes. Problem: Implication: A Single Step trap is taken when not expected. [. . . ] The glitch is not seen once the LVDS power supply is stable. Status: For the steppings affected, see the Summary Tables of Changes. BH38 Problem: Synchronous Reset of IA32_MPERF on IA32_APERF Overflow May Not Work When either the IA32_MPERF or IA32_APERF MSR (E7H, E8H) increments to its maximum value of 0xFFFF_FFFF_FFFF_FFFF, both MSRs are supposed to synchronously reset to 0x0 on the next clock. Due to this erratum, IA32_MPERF may not be reset when IA32_APERF overflows. Instead, IA32_MPERF may continue to increment without being reset. Due to this erratum, software cannot rely on synchronous reset of the IA32_MPERF register. [. . . ]