User manual INTEL CORE 2 DUO PROCESSOR E8000 DATASHEET

[. . . ] Intel® CoreTM2 Duo Processor E8000 and E7000 Series Datasheet June 2009 Document Number: 318732-006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. [. . . ] BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. These signals do not have on-die termination. Refer to Section 2. 6. 2 for termination requirements. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 17 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to Section 2. 8. 2. COMP[3:0] and COMP8 must be terminated to VSS on the system board using precision resistors. BPRI# Input BR0# Input/ Output BSEL[2:0] Output COMP[3:0], COMP8 Analog Datasheet 67 Land Listing and Signal Descriptions Table 26. Signal Description (Sheet 3 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. [. . . ] Recommended maximum internal chassis temperature for worst-case operating environment. When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. Notes X 30 1 Y = 35 - Z 38 NOTES: - 1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink. If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 32) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise. [. . . ]