User manual INTEL I7-620LE DATASHEET ADDENDUM

[. . . ] Intel® CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series Datasheet Addendum April 2010 Document Number: 323178-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Leg al Li nes and Dis clai mers Intel may make changes to specifications and product descriptions at any time, without notice. [. . . ] The SERR must not be enabled at the same time as the SMI for the same thermal sensor event. 0: Reporting of this condition via SERR messaging is disabled. Reserved SERR on LOCK to non-DRAM Memory (LCKERR): 1: The Processor will generate a DMI SERR special cycle whenever a CPU lock cycle is detected that does not hit DRAM. 0: Reporting of this condition via SERR messaging is disabled Reserved SERR on DRAM Throttle Condition (ERR): 0 = Reporting of this condition via SERR messaging is disabled. 1 = The memory controller generates a DMI SERR special cycle when a DRAM Read or Write Throttle condition occurs. Reserved SERR Multiple-Bit DRAM ECC Error (DMERR): 1: The Processor generates an SERR message over DMI when it detects a multiple-bit error reported by the DRAM controller. 0: Reporting of this condition via SERR messaging is disabled. For systems not supporting ECC this bit must be disabled. SERR on Single-bit ECC Error (DSERR): 1: The Processor generates an SERR special cycle over DMI when the DRAM controller detects a single bit error. 0: Reporting of this condition via SERR messaging is disabled. For systems that do not support ECC this bit must be disabled. Description 10 9 RO RW 0b 0b Core Core 8 7 RW RW 0b 0b Core Core 6:2 1 RO RW 00h 0b Core Core 0 RW 0b Core Intel® CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series Datasheet Addendum April 2010 74 Document Number: 323178-002 Processor Configuration Registers 6. 1. 4 SMICMD - SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: 0/0/0/PCI CC-CDh 0000h RO, RW; 16 bits This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. Note that one and only one message type can be enabled. SMI Command Registers Bit 15:12 11 Access RO RW Default Value 0h 0b RST/ PWR Core Core Reserved SMI on Processor Thermal Sensor Trip (TSTSMI): 1: A SMI DMI special cycle is generated by Processor when the thermal sensor trip requires an SMI. A thermal sensor trip point cannot generate more than one special cycle. 0: Reporting of this condition via SMI messaging is disabled. Reserved SMI on Multiple-Bit DRAM ECC Error (DMESMI): 1: The Processor generates an SMI DMI message when it detects a multiple-bit error reported by the DRAM controller. 0: Reporting of this condition via SMI messaging is disabled. For systems not supporting ECC this bit must be disabled. SMI on Single-bit ECC Error (DSESMI): 1: The Processor generates an SMI DMI special cycle when the DRAM controller detects a single bit error. 0: Reporting of this condition via SMI messaging is disabled. [. . . ] A value of 0 indicates that the table is not present (due to fixed VC priority). 23:8 7:0 RO RO 0000h 00h Core Core Reserved Reserved for VC Arbitration Capability (VCAC) 6. 3. 4PVCCTL - Port VC Control B/D/F/Type:0/6/0/MMR Address Offset:10C-10Dh Default Value:0000h Access: RO; RW; Size:16 bits Table 76. Bit 15:4 3:1 PVCCTL - Port VC Control Access RO RW Default Value 000h 000b RST/PWR Core Core Reserved VC Arbitration Select (VCAS) This field is programmed by software to the only possible value as indicated in the VC Arbitration Capability field. Since there is no other VC supported than the default, this field is reserved. Description 0 RO 0b Core Reserved for Load VC Arbitration Table Used for software to update the VC Arbitration Table when VC arbitration uses the VC Arbitration Table. As a VC Arbitration Table is never used by this component this field will never be used. 6. 3. 5VC0RCAP - VC0 Resource Capability B/D/F/Type:0/6/0/MMR Address Offset:110-113h Default Value:00000001h Access: RO; Size:32 bits Table 77. Bit 31:24 23 VC0RCAP - VC0 Resource Capability (Sheet 1 of 2) Access RO RO Default Value 00h 0b RST/PWR Core Core Description Reserved for Port Arbitration Table Offset Reserved Intel® CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505 Series April 2010 Datasheet Addendum Document Number: 323178-002 135 Processor Configuration Registers Table 77. Bit 22:16 15 VC0RCAP - VC0 Resource Capability (Sheet 2 of 2) Access RO RO Default Value 00h 0b RST/PWR Core Core Description Reserved for Maximum Time Slots Reject Snoop Transactions (RSNPT): Reject Snoop Transactions (RSNPT): 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. [. . . ]