User manual INTEL I7-900 DESKTOP PROCESSOR EXTREME EDITION DATASHEET VOLUME 1

[. . . ] Intel® CoreTM i7-900 Desktop Processor Extreme Edition Series and Intel® CoreTM i7-900 Desktop Processor Series Datasheet, Volume 1 February 2010 Document # 320834-004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. [. . . ] D2 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D3 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D4 D40 D41 D42 D43 D5 D6 D7 D8 D9 E1 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E2 E20 E21 E22 E23 RSVD DDR1_CLK_N[0] DDR1_MA[7] VDDQ DDR0_MA[3] RSVD DDR2_CKE[2] DDR1_CKE[2] VDDQ DDR1_RESET# VSS RSVD RSVD DDR0_RESET# VSS RSVD RSVD RSVD DDR0_DQ[27] VSS RSVD RSVD DDR0_DQ[24] DDR0_DQ[28] DDR0_DQ[29] VSS RSVD DDR1_DQ[38] DDR1_DQS_N[4] VSS DDR2_CS#[5] VSS DDR1_CS#[5] VDDQ RSVD RSVD DDR1_CAS# RSVD VDDQ DDR2_CS#[4] DDR0_CLK_N[2] DDR0_CLK_N[3] BPM#[7] DDR0_CLK_P[3] VDDQ DDR1_MA[8] DDR1_MA[11] PWR CMOS CLOCK CLOCK GTL CLOCK PWR CMOS CMOS O O O O O I/O O CMOS O CMOS CMOS GND CMOS GND CMOS PWR O O I/O I/O CMOS CMOS CMOS GND I/O I/O I/O CMOS GND I/O CMOS GND O CMOS CMOS PWR CMOS GND O O O CLOCK CMOS PWR CMOS O O O Pin Name BPM#[6] Buffer Type GTL Direction I/O 60 Datasheet Land Listing Table 4-2. Land Listing by Land Number (Sheet 19 of 29) Land No. E24 E25 E26 E27 E28 E29 E3 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E4 E40 E41 E42 E43 E5 E6 E7 E8 E9 F1 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F2 F20 F21 F22 F23 F24 F25 F26 F27 F28 RSVD VDDQ DDR1_CKE[1] RSVD RSVD DDR0_DQS_P[4] RSVD VDDQ DDR2_RESET# RSVD RSVD RSVD VSS RSVD DDR2_DQ[31] DDR2_DQS_P[3] DDR0_DQS_N[4] DDR2_DQS_N[3] VSS DDR0_DQ[18] DDR0_DQ[19] DDR1_DQ[34] VSS DDR1_DQS_P[4] DDR1_DQ[33] DDR1_DQ[32] DDR0_DQ[34] DDR1_DQ[36] DDR1_ODT[3] DDR0_ODT[0] DDR2_ODT[1] VDDQ DDR2_MA[13] DDR2_CAS# DDR2_BA[1] DDR0_CLK_P[2] VDDQ DDR0_DQ[39] DDR2_MA[4] RSVD DDR1_MA[5] RSVD VDDQ RSVD DDR1_MA[15] RSVD RSVD CMOS O PWR CMOS O CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS PWR CMOS CMOS CMOS CLOCK PWR CMOS CMOS I/O O O O O O I/O I/O I/O I/O I/O O O O I/O I/O I/O I/O I/O I/O I/O GND PWR CMOS O CMOS I/O PWR CMOS O Pin Name DDR1_MA[12] Buffer Type CMOS Direction O Table 4-2. Land Listing by Land Number (Sheet 20 of 29) Land No. F29 F3 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F4 F40 F41 F42 F43 F5 F6 F7 F8 F9 G1 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G2 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G3 G30 G31 G32 VSS DDR0_DQ[38] RSVD RSVD RSVD RSVD VSS RSVD RSVD RSVD DDR2_DQ[30] VSS VSS DDR2_DQ[25] DDR0_DQS_P[2] DDR0_DQ[23] DDR0_DQ[22] DDR1_DQ[35] DDR1_DQ[39] RSVD RSVD VSS DDR0_DQ[44] DDR2_DQ[37] DDR2_DQ[36] VSS DDR1_WE# DDR1_RAS# DDR0_CS#[0] DDR2_CS#[0] VDDQ DDR2_MA[2] DDR1_CLK_P[1] VSS DDR1_CLK_N[1] DDR2_CLK_N[2] VDDQ DDR2_MA[12] DDR1_MA[9] DDR2_MA[15] DDR2_CKE[1] VDDQ RSVD RSVD DDR0_DQ[35] RSVD RSVD VSS GND CMOS I/O GND CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS PWR CMOS CLOCK GND CLOCK CLOCK PWR CMOS CMOS CMOS CMOS PWR O O O O O O O O O O O O I/O I/O I/O CMOS GND GND CMOS CMOS CMOS CMOS CMOS CMOS I/O I/O I/O I/O I/O I/O I/O GND Pin Name Buffer Type GND CMOS I/O Direction Datasheet 61 Land Listing Table 4-2. Land Listing by Land Number (Sheet 21 of 29) Land No. G33 G34 G35 G36 G37 G38 G39 G4 G40 G41 G42 G43 G5 G6 G7 G8 G9 H1 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H2 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H3 H30 H31 H32 H33 H34 H35 H36 H37 RSVD RSVD RSVD RSVD VSS RSVD DDR2_DQ[29] DDR1_DQ[42] DDR2_DQ[24] DDR0_DQS_N[2] VSS RSVD DDR1_DQ[46] DDR1_DQS_N[5] VSS DDR1_DQ[37] DDR1_DQ[44] DDR0_DQ[41] VSS RSVD DDR2_DQ[38] DDR2_DQ[34] DDR1_MA[10] VDDQ RSVD DDR2_MA[10] DDR1_CLK_P[3] DDR1_CLK_N[3] DDR0_DQ[40] VDDQ DDR2_CLK_P[2] DDR2_MA[9] DDR2_MA[11] DDR2_MA[14] VDDQ DDR1_MA[14] DDR1_BA[2] DDR1_CKE[0] RSVD DDR0_DQ[45] VSS RSVD RSVD DDR1_DQ[24] DDR1_DQ[29] VSS DDR1_DQ[23] DDR2_DQ[27] CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O CMOS GND I/O CMOS CLOCK CLOCK CMOS PWR CLOCK CMOS CMOS CMOS PWR CMOS CMOS CMOS O O O O O O O O O O I/O CMOS CMOS CMOS PWR I/O I/O O CMOS CMOS GND CMOS CMOS CMOS GND I/O I/O I/O I/O I/O CMOS CMOS CMOS CMOS GND I/O I/O I/O I/O GND Pin Name Buffer Type Direction Table 4-2. Land Listing by Land Number (Sheet 22 of 29) Land No. H38 H39 H4 H40 H41 H42 H43 H5 H6 H7 H8 H9 J1 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J2 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J3 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J4 J40 J41 RSVD DDR2_DQ[28] DDR1_DQ[43] VSS DDR0_DQ[16] RSVD DDR0_DQ[17] VSS DDR1_DQS_P[5] RSVD DDR1_DQ[40] DDR1_DQ[45] RSVD DDR2_DQS_P[4] RSVD DDR2_DQ[33] VSS DDR1_MA[0] RSVD DDR1_MA[1] DDR1_MA[2] VDDQ DDR0_CLK_P[0] RSVD DDR2_MA[3] DDR2_CLK_N[0] DDR2_CLK_P[0] VDDQ DDR2_MA[7] RSVD DDR2_CKE[0] DDR1_MA[6] VDDQ RSVD VSS RSVD RSVD DDR1_DQ[27] VSS DDR1_DQ[28] DDR1_DQ[19] DDR1_DQ[22] DDR2_DQ[26] VSS DDR2_DQ[19] DDR1_DQ[52] DDR2_DQ[18] DDR0_DQ[21] CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O GND CMOS CMOS PWR O O CMOS CLOCK CLOCK PWR CMOS O O O O CMOS CMOS PWR CLOCK O O O CMOS GND CMOS O I/O CMOS I/O CMOS CMOS I/O I/O CMOS GND CMOS I/O I/O CMOS CMOS GND CMOS I/O I/O I/O Pin Name Buffer Type Direction 62 Datasheet Land Listing Table 4-2. Land Listing by Land Number (Sheet 23 of 29) Land No. J42 J43 J5 J6 J7 J8 J9 K1 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K2 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K3 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K4 K40 K41 K42 K43 K5 K6 K7 VSS DDR1_DQ[47] DDR1_DQ[41] RSVD VSS DDR2_DQS_N[4] VSS DDR2_DQ[41] VSS DDR2_DQ[32] DDR1_BA[1] DDR2_CS#[1] RSVD VDDQ DDR2_MA[1] DDR1_CLK_P[2] DDR0_CLK_N[0] DDR0_DQS_P[5] DDR2_CLK_N[1] VDDQ DDR2_MA[6] DDR2_MA[5] RSVD RSVD VDDQ RSVD DDR1_MA[4] RSVD DDR0_DQS_N[5] DDR1_DQ[31] VSS DDR1_DQ[26] RSVD RSVD DDR1_DQ[18] VSS RSVD DDR2_DQ[23] DDR2_DQS_N[2] DDR1_DQ[48] DDR2_DQS_P[2] VSS DDR0_DQ[10] DDR0_DQ[11] DDR1_DQ[49] VSS DDR2_DQS_N[5] CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O I/O I/O I/O CMOS GND I/O CMOS CMOS GND CMOS I/O I/O I/O CMOS O PWR PWR CMOS CLOCK CLOCK CMOS CLOCK PWR CMOS CMOS O O O O O I/O O GND CMOS GND CMOS GND CMOS CMOS CMOS I/O O O I/O I/O Pin Name DDR0_DQ[20] Buffer Type CMOS GND CMOS CMOS I/O I/O Direction I/O Table 4-2. Land Listing by Land Number (Sheet 24 of 29) Land No. K8 K9 L1 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L2 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L3 L30 L31 L32 L33 L34 L35 L36 L37 L38 L39 L4 L40 L41 L42 L43 L5 L6 L7 L8 L9 M1 M10 M11 RSVD RSVD DDR0_DQ[42] DDR2_DQ[40] DDR2_DQ[44] DDR2_DQ[39] DDR2_DQ[35] VDDQ RSVD DDR2_ODT[0] RSVD DDR1_CLK_N[2] VDDQ DDR0_DQ[47] DDR2_CLK_P[1] DDR2_CLK_N[3] DDR2_CLK_P[3] DDR_VREF VDDQ DDR2_MA[8] DDR2_BA[2] DDR2_CKE[3] DDR1_MA[3] VSS DDR0_DQ[46] DDR1_DQS_P[3] DDR1_DQS_N[3] DDR1_DQ[30] DDR1_DQ[25] VSS DDR1_DQS_P[2] DDR1_DQS_N[2] RSVD RSVD VSS VSS DDR2_DQ[22] DDR0_DQS_P[1] DDR0_DQ[15] DDR0_DQ[14] DDR1_DQS_N[6] DDR1_DQS_P[6] DDR2_DQS_P[5] DDR2_DQ[46] VSS DDR0_DQ[43] DDR2_DQ[45] VCC GND GND CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLOCK PWR CMOS CLOCK CLOCK CLOCK Analog PWR CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O I/O I/O I/O O O O O I/O O O O I O CMOS O CMOS CMOS CMOS CMOS CMOS PWR I/O I/O I/O I/O I/O Pin Name Buffer Type Direction Datasheet 63 Land Listing Table 4-2. Land Listing by Land Number (Sheet 25 of 29) Land No. M12 M13 M14 M15 M16 M17 M18 M19 M2 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M3 M30 M31 M32 M33 M34 M35 M36 M37 M38 M39 M4 M40 M41 M42 M43 M5 M6 M7 M8 M9 N1 N10 N11 N2 N3 N33 N34 N35 VSS VCC VSS VCC VSS VDDQ VSS VCC VSS VSS VCC VSS VCC VSS VCC VSS VDDQ VSS VCC DDR0_DQ[52] VSS VCC VSS VCC DDR1_DQ[17] DDR1_DQ[16] DDR1_DQ[21] VSS RSVD DDR2_DQ[16] RSVD DDR2_DQ[17] DDR0_DQS_N[1] VSS RSVD RSVD DDR1_DQ[53] VSS DDR2_DQ[47] DDR2_DQ[42] DDR0_DQ[48] VSS VCC DDR0_DQ[49] DDR0_DQ[53] VCC DDR1_DQ[20] VSS CMOS GND CMOS CMOS CMOS GND PWR CMOS CMOS PWR CMOS GND I/O I/O I/O I/O I/O I/O I/O CMOS CMOS GND I/O I/O CMOS I/O Pin Name Buffer Type GND PWR GND PWR GND PWR GND PWR GND GND PWR GND PWR GND PWR GND PWR GND PWR CMOS GND PWR GND PWR CMOS CMOS CMOS GND I/O I/O I/O I/O Direction Table 4-2. Land Listing by Land Number (Sheet 26 of 29) Land No. N36 N37 N38 N39 N4 N40 N41 N42 N43 N5 N6 N7 N8 N9 P1 P10 P11 P2 P3 P33 P34 P35 P36 P37 P38 P39 P4 P40 P41 P42 P43 P5 P6 P7 P8 P9 R1 R10 R11 R2 R3 R33 R34 R35 R36 R37 R38 R39 Pin Name DDR2_DQ[21] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[11] RSVD VSS DDR0_DQ[8] RSVD DDR0_DQ[9] VSS DDR2_DQ[49] DDR2_DQ[53] DDR2_DQ[52] DDR2_DQ[43] RSVD DDR2_DQ[51] VSS RSVD VSS VSS DDR1_DQ[8] DDR1_DQ[9] RSVD RSVD VSS DDR1_DQ[10] RSVD DDR2_DQ[20] DDR0_DQ[13] DDR0_DQ[12] VSS DDR2_DQS_N[6] DDR2_DQS_P[6] DDR2_DQ[48] VSS DDR2_DQ[50] VSS DDR2_DQ[54] VCC DDR0_DQS_P[6] DDR0_DQS_N[6] VCC DDR1_DQ[12] DDR1_DQ[13] VSS DDR1_DQS_N[1] DDR1_DQS_P[1] DDR2_DQ[10] CMOS CMOS CMOS GND CMOS CMOS CMOS GND CMOS GND CMOS PWR CMOS CMOS PWR CMOS CMOS GND CMOS CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND CMOS I/O GND GND CMOS CMOS I/O I/O CMOS GND I/O CMOS GND CMOS CMOS CMOS CMOS I/O I/O I/O I/O I/O GND CMOS I/O Buffer Type CMOS CMOS CMOS CMOS Direction I/O I/O I/O I/O 64 Datasheet Land Listing Table 4-2. Land Listing by Land Number (Sheet 27 of 29) Land No. R4 R40 R41 R42 R43 R5 R6 R7 R8 R9 T1 T10 T11 T2 T3 T33 T34 T35 T36 T37 T38 T39 T4 T40 T41 T42 T43 T5 T6 T7 T8 T9 U1 U10 U11 U2 U3 U33 U34 U35 U36 U37 U38 U39 U4 U40 U41 U42 Pin Name DDR0_DQ[54] DDR2_DQ[15] VSS DDR0_DQ[3] DDR0_DQ[2] DDR1_DQ[50] VSS DDR1_DQ[55] DDR1_DQ[54] DDR2_DQ[55] DDR0_DQ[50] DDR2_DQ[58] VCC DDR0_DQ[51] DDR0_DQ[55] VCC VSS RSVD DDR2_DQ[11] DDR2_DQS_P[1] DDR2_DQS_N[1] VSS VSS RSVD DDR2_DQ[14] DDR0_DQ[7] DDR0_DQS_P[0] DDR1_DQ[51] DDR2_DQ[60] DDR2_DQ[61] DDR2_DQS_N[7] VSS DDR0_DQ[60] DDR2_DQ[59] RSVD VSS DDR0_DQ[61] VCCPLL DDR2_DQ[4] RSVD DDR2_DQ[3] VSS DDR2_DQ[8] DDR2_DQ[9] DDR0_DQ[56] RSVD DDR0_DQ[6] VSS CMOS GND I/O CMOS GND CMOS CMOS CMOS I/O I/O I/O I/O GND CMOS PWR CMOS I/O I/O CMOS CMOS CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O CMOS CMOS CMOS GND GND I/O I/O I/O Buffer Type CMOS CMOS GND CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS PWR CMOS CMOS PWR GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Direction I/O I/O Table 4-2. Land Listing by Land Number (Sheet 28 of 29) Land No. U43 U5 U6 U7 U8 U9 V1 V10 V11 V2 V3 V33 V34 V35 V36 V37 V38 V39 V4 V40 V41 V42 V43 V5 V6 V7 V8 V9 W1 W10 W11 W2 W3 W33 W34 W35 W36 W37 W38 W39 W4 W40 W41 W42 W43 W5 W6 W7 Pin Name DDR0_DQS_N[0] DDR2_DQ[56] DDR2_DQ[57] VSS DDR2_DQS_P[7] DDR2_DQ[63] DDR0_DQ[57] VSS RSVD RSVD RSVD VCCPLL DDR2_DQ[5] VSS DDR2_DQ[2] DDR2_DQ[6] DDR2_DQ[7] DDR2_DQ[13] DDR0_DQ[62] VSS DDR0_DQ[1] RSVD RSVD VSS RSVD RSVD DDR2_DQ[62] DDR1_DQ[60] DDR0_DQS_N[7] DDR1_DQ[59] VCC DDR0_DQS_P[7] VSS VCCPLL DDR2_DQ[0] DDR2_DQ[1] DDR2_DQS_N[0] DDR2_DQS_P[0] VSS DDR2_DQ[12] DDR0_DQ[63] DDR0_DQ[4] DDR0_DQ[0] DDR0_DQ[5] VSS DDR1_DQ[61] DDR1_DQ[56] DDR1_DQ[57] CMOS CMOS CMOS CMOS PWR CMOS GND PWR CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND PWR CMOS GND CMOS CMOS CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O I/O I/O Buffer Type CMOS CMOS CMOS GND CMOS CMOS CMOS GND I/O I/O I/O Direction I/O I/O I/O Datasheet 65 Land Listing Table 4-2. Land Listing by Land Number (Sheet 29 of 29) Land No. [. . . ] The air temperature entering the fan should be kept below 40 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator. Datasheet 93 Boxed Processor Specifications Figure 8-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) Figure 8-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) 94 Datasheet Boxed Processor Specifications 8. 4. 2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. [. . . ]