User manual INTEL LGA1155 SOCKET THERMAL MECHANICAL SPECIFICATIONS AND DESIGN GUIDELINES 01-2011

[. . . ] 2nd Generation Intel® CoreTM Processor Family Desktop and LGA1155 Socket Thermal Mechanical Specifications and Design Guidelines (TMSDG) Supporting the Intel® CoreTM i7, i5 and i3 Desktop Processor January 2011 Document Number #: 324644-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. [. . . ] Transition of the VID code will occur first, to insure proper operation as the frequency is increased. Refer to Figure 6-6 for an illustration of this ordering. 54 Thermal/Mechanical Specifications and Design Guidelines Thermal Specifications Figure 6-6. Frequency and Voltage Ordering Temperature fMAX f1 f2 Frequency VIDfMAX VIDf1 VIDf2 VID PROCHOT# 6. 2. 2. 2 Clock Modulation Clock modulation is a second method of thermal control available to the processor. Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle that should reduce power dissipation by about 50% (typically a 30-50% duty cycle). Clocks often will not be off for more than 32 microseconds when the TCC is active. Cycle times are independent of processor frequency. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. It is possible for software to initiate clock modulation with configurable duty cycles. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. 6. 2. 2. 3 Immediate Transition to combined TM1 and TM2 As mentioned above, when the TCC is activated the processor will sequentially step down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature. If the temperature continues to increase and exceeds the TCC activation temperature by approximately 5 oC before the lowest ratio/VID combination has been reached, then the processor will immediately transition to the combined TM1/TM2 condition. The processor will remain in this state until the temperature has dropped below the TCC activation point. Once below the TCC activation temperature, TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio/VID state. Thermal/Mechanical Specifications and Design Guidelines 55 Thermal Specifications 6. 2. 2. 4 Critical Temperature Flag If TM2 is unable to reduce the processor temperature, then TM1 will be also be activated. TM1 and TM2 will then work together to reduce power dissipation and temperature. It is expected that only a catastrophic thermal solution failure would create a situation where both TM1 and TM2 are active. If TM1 and TM2 have both been active for greater than 20ms and the processor temperature has not dropped below the TCC activation point, then the Critical Temperature Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator of a catastrophic thermal solution failure and that the processor cannot reduce its temperature. Unless immediate action is taken to resolve the failure, the processor will probably reach the Thermtrip temperature (see Section 6. 2. 3 Thermtrip Signal) within a short time. In order to prevent possible permanent silicon damage, Intel recommends removing power from the processor within ½ second of the Critical Temperature Flag being set 6. 2. 2. 5 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled (note it must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Although the PROCHOT# signal is an output by default, it may be configured as bidirectional. When configured in bi-directional mode, it is either an output indicating the processor has exceeded its TCC activation temperature or it can be driven from an external source (such as, a voltage regulator) to activate the TCC. [. . . ] LGA 1156 & 1155 HS BACKPLATE KEEP-IN VOLUME ENCOMPASS THE BACKPLATE NOMINAL VOLUME AND ALLOWANCES FOR SIZE TOLERANCES. THERMAL/MECHANICAL COMPONENT DEVELOPERS SHALL DESIGN TO THE OUTSIDE OF SOCKET H1 ILM BACKPLATE 4 WITH CLEARANCE MARGINS. REFERENCE DRAWINGS: E20847 - LGA 1156 & 1155 ILM BACKPLATE E21320 - LGA 1156 & 1155 ILM & PROCESSOR KEEPIN 4 OUTLINE OF LGA 1156 & 1155 ILM BACKPLATE FOR REFERENCE ONLY. DIMENSIONS ARE IN MILLIMETERS Heat Sink Back Plate Keep In Zone 2X 75 B B 2X 25. 81 1 2X 37. 54 1 72. 75 13. 9 27. 81 78. 25 95 26 MAX 2. 54 2X 75 26 MAX 19. 19 36 95 DEPARTMENT R 4 TITLE 2200 MISSION COLLEGE BLVD. [. . . ]