User manual JETWAY 866ASR2C

[. . . ] 866AS/866AS-R/866ASE AMD Socket A Athlon/Duron sG oGG G03-866ASR2C 2001 ~ 9 Ӽ: Athlon M Duron O AMD qUӼСCLӼФΦW٬ݨ qҦC ϥΪ̻ UT ѨM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 866AS/866AS-R/866ASE DO² DOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] The settings are: Enabled and Disabled. 3-6-1 DRAM Timing Settings CMOS Setup Utility Copyright(C) 1984-2001 Award Software DRAM Timing Settings Auto Configuration RAS Active Time RAS Precharge Time RAS to CAS Delay CAS Latency Bank Interleave DRAM Command Rate Optimized 6T 3T 3T 2. 5T 4 Bank 2T Command Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults RAS Active Time This field let's you insert a timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read from, or refreshed. Fast gives faster performance; and 28 Slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system. RAS Precharge Time If an insufficient number of cycles is allowed for the RAS to accumulate its charge before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast gives faster performance; and Slow gives more stable performance. This field applies only when synchronous DRAM is installed in the system. CAS Latency When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The settings are: 2T and 2. 5T. 3-6-2 AGP Timing Settings CMOS Setup Utility Copyright(C) 1984-2001 Award Software AGP Timing Settings AGP AGP AGP AGP AGP AGP AGP CPU AGP Transfer Aperture Size Mode Driving Control Driving Value Fast Write Master 1 WS Write Master 1 WS Read to AGP Post Write Delay Transaction 128M Auto Auto DA Disabled Enabled Enabled Disabled Disabled Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults Note: Change these settings only if you are familiar with the chipset. 3-6-3 PCI Timing Settings CMOS Setup Utility Copyright(C) 1984-2001 Award Software PCI Timing Settings PCI PCI CPU PCI Master 1 WS Write Master 1 WS Read to AGP Post Write Delay Transaction Disabled Disabled Disabled Disabled Item Help Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F5:Previous Values F6:Optimized Defaults F1:General Help F7:Standard Defaults PCI Delay Transaction 29 The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification version 2. 1. The settings are: Enabled and Disabled. 3-7 Integrated Peripherals CMOS Setup Utility Copyright(C) 1984-2001 Award Software Integrated Peripherals > OnChip IDE Function > OnChip Device Function > Onboard Super IO Function Init Display First Press Enter Press Enter Press Enter PCI Slot Item Help Menu Level > Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults OnChip IDE Function Please refer to section 3-7-1 OnChip Device Function Please refer to section 3-7-2 Onboard Super IO Function Please refer to section 3-7-3 Init Display First This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings are: PCI Slot, AGP Slot. 3-7-1 OnChip IDE Function CMOS Setup Utility Copyright(C) 1984-2001 Award Software OnChip IDE Function OnChip IDE Channel0 OnChip IDE Channel1 Enabled Enabled Item Help 30 Primary Master PIO Primary Slave PIO Secondary Master PIO Secondary Slave PIO Primary Master UDMA Primary Slave UDMA Secondary Master UDMA Secondary Slave UDMA IDE 32-bit Transfer Mode IDE HDD Block Mode IDE Prefetch Mode Delay For HDD (Secs) Auto Auto Auto Auto Auto Auto Auto Auto Enabled Enabled Enabled 0 Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults OnChip IDE Channal0/Channel1 The integrated peripheral controller contains an IDE interface with support for two IDE channels. Select Enabled to activate each channel separately. Primary/Secondary Master/Slave PIO The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4) for each of the four IDE devices that the onboard IDE interface supports. Modes 0 through 4 provide successively increased performance. In Auto mode, the system automatically determines the best mode for each device. The settings are: Auto, Mode 0, Mode 1, Mode 2, Mode 3, Mode 4. Primary/Secondary Master/Slave UDMA Ultra DMA/33 implementation is possible only if your IDE hard drive supports it and the operating environment includes a DMA driver (Windows 95 OSR2 or a third-party IDE bus master driver). If your hard drive and your system software both support Ultra DMA/33 and Ultra DMA/66, select Auto to enable BIOS support. IDE HDD Block Mode Block mode is also called block transfer, multiple commands, or multiple sector read/write. If your IDE hard drive supports block mode (most new drives do), select Enabled for automatic detection of the optimal number of block read/writes per sector the drive can support. The settings are: Enabled, Disabled. 3-7-2 OnChip Device Function CMOS Setup Utility Copyright(C) 1984-2001 Award Software OnChip Device Function AC97 Sound Device Game Port Address Auto 201 Item Help 31 Midi Port Address Midi Port IRQ AC97 Modem Device USB Host Controller USB Keyboard Legacy Support Disabled 10 Auto Enabled Disabled Menu Level >> Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5:Previous Values F6:Optimized Defaults F7:Standard Defaults AC97 Sound Device This item allows you to decide to enable/disable the KT-266 chipset family to support AC97 Audio. Game Port Address/Midi Port Address This will determine which Address the Game Port/Midi Port will use. [. . . ] M۰˴ާ@tλyA OK"AYi}lwXʵ{AA "NEXT"AY|X{vTC 3. tθ߰ OKC " Remove old device driver"A 4. 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