User manual KINGSTON KVR533D2S8F41G MEMORY MODULE SPECIFICATIONS

[. . . ] Memory Module Specifications KVR533D2S8F4/1G 1GB 128M x 72-Bit PC2-4200 CL4 ECC 240-Pin FBDIMM Description: This document describes ValueRAM's 1GB (128M x 72-bit) PC2-4200 CL4 SDRAM (Synchronous DRAM) "fully buffered" ECC "single rank" memory module. This module is based on nine 128M x 8-bit 533MHz DDR2 FBGA components. [. . . ] Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility Absolute Maximum Ratings Symbol VIN, VOUT VCC VDD VTT TSTG TCASE Parameter Voltage on any pin relative to V Voltage V DD pin relative to Vss Voltage on V TT pin relative to V SS Storage temperature DDR2 SDRAM device operat ing temperature (Ambient) AMB device operating temperature (Ambient) SS MIN -0. 3 -0. 3 -0. 5 -0. 5 -55 0 0 MAX 1. 75 1. 75 2. 3 2. 3 100 95 (1) 110 Units V V V V °C °C °C Voltage on V CC pin relative to V SS Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3. 9 µs. VALUERAM0841-001. A00 Page 3 TECHNOLOGY Functional Block Diagram: S0 DQS0 DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DQS4 DQS4 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS8 DQS8 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS DM/ NU/ RDQS RDQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 PN0-PN13 PN0-PN13 PS0-PS9 PS0-PS9 DQ0-DQ63 CB0-CB7 DQS0-DQS17 DQS0-DQS8 SCL SDA SA1-SA2 SA0 RESET SCK/SCK SN0-SN13 SN0-SN13 SS0-SS9 SS0-SS9 A M B S0 -> CS (all SDRAMs) CKE0 -> CKE (all SDRAMs) ODT -> ODT (all SDRAMs) BA0-BA2 (all SDRAMs) A0-A15 (all SDRAMs) RAS (all SDRAMs) CAS (all SDRAMs) WE (all SDRAMs) CK/CK (all SDRAMs) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 VTT VCC 22 Terminators AMB SPD, AMB D0-D8, AMB D0-D8 D0-D8, SPD, AMB 825 All address/command/control/clock VTT VDDSPD VDD trol/clock Notes: 1. DQ-to-I/O wiring may be changed within a byte. There are two physical copies of each address/command/con- Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA VREF VSS VALUERAM0841-001. A00 Page 4 TECHNOLOGY Architecture: Advanced Memory Buffer Pin Description: Pin Name Pin Description Count FB-DIMM Channel Signals SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] FBDRES System Clock Input, positive line System Clock Input, negative line Primary Northbound Data, positive lines Primary Northbound Data, negative lines Primary Southbound Data, positive lines Primary Southbound Data, negative lines Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines To an external precision calibration resistor connected to Vcc 99 1 1 14 14 10 10 14 14 10 10 1 DDR2 Interface Signals DQS[8:0] DQS[8:0] DQS[17:9]/DM[8:0] DQS[17:9] DQ[63:0] CB[7:0] A[15:0]A, A[15:0]B BA[2:0]A, BA[2:0]B RASA, RASB CASA, CASB WEA, WEB ODTA, ODTB CS[1:0]A, CS[1:0]B CLK[3:0] CLK[3:0] DDRC_C14 DDRC_B18 DDRC_C18 DDRC_B12 DDRC_C12 Data Strobes, positive lines Data Strobes, negative lines Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. Data Strobes (x4 DRAM only), negative lines Data Checkbits Addresses. A10 is part of the pre-charge command Bank Addresses Part of command, with CAS, WE, and CS[1:0]. Part of command, with RAS, WE, and CS[1:0]. Part of command, with RAS, CAS, and CS[1:0]. On-die Termination Enable Chip Select (one per rank) 175 9 9 9 9 64 8 32 6 2 2 2 2 4 4 CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank) CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out4 put disabled when not in use. Negative lines for CLK[3:0] DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18. DDR Compensation: Resistor connected to common return pin DDRC_C14 DDR Compensation: Resistor connected to common return pin DDRC_C14 DDR Compensation: Resistor connected to VSS DDR Compensation: Resistor connected to VDD 4 1 1 1 1 1 VALUERAM0841-001. A00 Page 5 TECHNOLOGY Advanced Memory Buffer Pin Description: SPD Bus Interface Signals SCL SDA SA[2:0] Serial Presence Detect (SPD) Clock Input SPD Data Input / Output SPD Address Inputs, also used to select the DIMM number in the AMB 5 1 1 3 Miscellaneous Signals PLLTSTO VCCAPLL VSSAPLL TEST_pin# TESTLO_pin# BFUNC RESET NC RFU PLL Clock Observability Output Analog VCC for the PLL. [. . . ] TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production DIMMs with a direct connection to ground. VALUERAM0841-001. A00 Page 6 TECHNOLOGY Package Dimensions: TECHNOLOGY FBGA DDR2 SDRAM FBGA DDR2 SDRAM Advanced Memory Buffer AMB FBGA DDR2 SDRAM FBGA DDR2 SDRAM (Units = millimeters) 0. 346 (8. 8) MAX with heat sink TECHNOLOGY w/ Heat Sink Assembly T E C H N O L O G Y VALUERAM0841-001. A00 FBGA DDR2 SDRAM FBGA DDR2 SDRAM FBGA DDR2 SDRAM FBGA DDR2 SDRAM FBGA DDR2 SDRAM Units: inches (millimeters) 45°x 0. 0071(0. 18) 0. 047 (1. 19) 0. 042 (1. 06) 0. 042 (1. 06) 0. 054 (1. 37) 0. 046 (1. 17) Detail A Page 7 [. . . ]