User manual KINGSTON KVR667D2D4F54G MEMORY MODULE SPECIFICATIONS

[. . . ] Memory Module Specifications KVR667D2D4F5/4G 4GB 512M x 72-Bit PC2-5300 CL5 ECC 240-Pin FBDIMM Description: This document describes ValueRAM's 4GB (512M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully buffered" ECC "dual rank" memory module. This module is based on eighteen stacked 512M x 4-bit (thirty-six 256M x 4-bit) 667MHz DDR2 FBGA components. [. . . ] Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility Absolute Maximum Ratings Symbol VIN, VOUT VCC VDD VTT TSTG TCASE Parameter Voltage on any pin relative to V Voltage V DD pin relative to Vss Voltage on V TT pin relative to V SS Storage temperature DDR2 SDRAM device operat ing temperature (Ambient) AMB device operating temperature (Ambient) SS MIN -0. 3 -0. 3 -0. 5 -0. 5 -55 0 0 MAX 1. 75 1. 75 2. 3 2. 3 100 95 (1) 110 Units V V V V °C °C °C Voltage on V CC pin relative to V SS Note: (1) Above 85°C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3. 9 µs. VALUERAM0530-001. A00 Page 3 TECHNOLOGY Functional Block Diagram: VSS S1 S0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQS1 DM CS DQS DQS DM DQS9 DQS9 CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 D0 I/O 0 I/O 1 I/O 2 I/O 3 D18 DQ4 DQ5 DQ6 DQ7 DQS10 DQS10 CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D9 I/O 0 I/O 1 I/O 2 I/O 3 D27 DM DQ8 DQ9 DQ10 DQ11 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 DQS8 CB0 CB1 CB2 CB3 PN0-PN13 PN0-PN13 PS0-PS9 PS0-PS9 CS DQS DQS DM CS DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 DM D1 I/O 0 I/O 1 I/O 2 I/O 3 DM D19 DQ12 DQ13 DQ14 DQ15 DQS11 DQS11 CS DQS DQS DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D10 I/O 0 I/O 1 I/O 2 I/O 3 DM D28 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D2 I/O 0 I/O 1 I/O 2 I/O 3 DM D20 DQ20 DQ21 DQ22 DQ23 DQS12 DQS12 DQ28 DQ29 DQ30 DQ31 DQS13 DQS13 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D11 I/O 0 I/O 1 I/O 2 I/O 3 DM D29 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS CS DQS DQS D21 I/O 0 I/O 1 I/O 2 I/O 3 DM D12 I/O 0 I/O 1 I/O 2 I/O 3 DM D30 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D4 I/O 0 I/O 1 I/O 2 I/O 3 DM D22 DQ36 DQ37 DQ38 DQ39 DQS14 DQS14 DQ44 DQ45 DQ46 DQ47 DQS15 DQS15 DQ52 DQ53 DQ54 DQ55 DQS16 DQS16 DQ60 DQ61 DQ62 DQ63 DQS17 DQS17 CB4 CB5 CB6 CB7 33 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D13 I/O 0 I/O 1 I/O 2 I/O 3 DM D31 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D5 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS CS DQS DQS D23 I/O 0 I/O 1 I/O 2 I/O 3 DM D14 I/O 0 I/O 1 I/O 2 I/O 3 DM D32 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D6 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS CS DQS DQS D24 I/O 0 I/O 1 I/O 2 I/O 3 DM D15 I/O 0 I/O 1 I/O 2 I/O 3 DM D33 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D7 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS CS DQS DQS D25 I/O 0 I/O 1 I/O 2 I/O 3 DM D16 I/O 0 I/O 1 I/O 2 I/O 3 DM D34 CS DQS DQS CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D8 I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DQS CS DQS DQS D26 I/O 0 I/O 1 I/O 2 I/O 3 D17 VTT VCC VDDSPD I/O 0 I/O 1 I/O 2 I/O 3 D35 Terminators AMB SPD, AMB D0-D35, AMB D0-D35 D0-D35, SPD, AMB SN0-SN13 SN0-SN13 SS0-SS9 SS0-SS9 All address/command/control/clock Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 VTT SDA A M B SCL SDA SA1-SA2 SA0 RESET SCK/SCK S0 -> CS (D0-D17) CKE0 -> CKE (D0-D17) S1 -> CS (D18-D35) CKE1 -> CKE (D18-D35) ODT -> ODT0 (all SDRAMs) BA0-BA2 (all SDRAMs) A0-A15 (all SDRAMs) RAS (all SDRAMs) CAS (all SDRAMs) WE (all SDRAMs) CK/CK (all SDRAMs) VDD VREF 3. There are four physical copies of each clock VSS Notes: 1. DQ-to-I/O wiring may be changed within a nibble 2. There are two physical copies of each address/command/control 825 VALUERAM0530-001. A00 Page 4 TECHNOLOGY Architecture: Advanced Memory Buffer Pin Description: Pin Name Pin Description Count FB-DIMM Channel Signals SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] FBDRES System Clock Input, positive line System Clock Input, negative line Primary Northbound Data, positive lines Primary Northbound Data, negative lines Primary Southbound Data, positive lines Primary Southbound Data, negative lines Secondary Northbound Data, positive lines Secondary Northbound Data, negative lines Secondary Southbound Data, positive lines Secondary Southbound Data, negative lines To an external precision calibration resistor connected to Vcc 99 1 1 14 14 10 10 14 14 10 10 1 DDR2 Interface Signals DQS[8:0] DQS[8:0] DQS[17:9]/DM[8:0] DQS[17:9] DQ[63:0] CB[7:0] A[15:0]A, A[15:0]B BA[2:0]A, BA[2:0]B RASA, RASB CASA, CASB WEA, WEB ODTA, ODTB CS[1:0]A, CS[1:0]B CLK[3:0] CLK[3:0] DDRC_C14 DDRC_B18 DDRC_C18 DDRC_B12 DDRC_C12 Data Strobes, positive lines Data Strobes, negative lines Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes. Data Strobes (x4 DRAM only), negative lines Data Checkbits Addresses. A10 is part of the pre-charge command Bank Addresses Part of command, with CAS, WE, and CS[1:0]. Part of command, with RAS, WE, and CS[1:0]. Part of command, with RAS, CAS, and CS[1:0]. On-die Termination Enable Chip Select (one per rank) 175 9 9 9 9 64 8 32 6 2 2 2 2 4 4 CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank) CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be out4 put disabled when not in use. Negative lines for CLK[3:0] DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18. [. . . ] TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs: each pin should have a zero ohm resistor pulldown to ground, and an unpopulated resistor pullup to VCC. These resistors can be replaced on production DIMMs with a direct connection to ground. VALUERAM0530-001. A00 Page 6 TECHNOLOGY Package Dimensions: Advanced Memory Buffer AMB TECHNOLOGY (Units = millimeters) Units: inches (millimeters) 45°x 0. 0071(0. 18) 0. 047 (1. 19) 0. 042 (1. 06) 0. 042 (1. 06) Detail A VALUERAM0530-001. A00 Page 7 [. . . ]