User manual LON EN29F040A

[. . . ] EN29F040A EN29F040A 4 Megabit (512K x 8-bit) Flash Memory FEATURES · 5. 0V operation for read/write/erase operations · Fast Read Access Time - 45ns, 55ns, 70ns, and 90ns · Sector Architecture: 8 uniform sectors of 64Kbytes each Supports full chip erase Individual sector erase supported Sector protection: Hardware locking of sectors to prevent program or erase operations within individual sectors High performance program/erase speed Byte program time: 10µs typical Sector erase time: 500ms typical Chip erase time: 3. 5s typical · JEDEC Standard program and erase commands · JEDEC standard DATA polling and toggle bits feature · Single Sector and Chip Erase · Sector Unprotect Mode · Embedded Erase and Program Algorithms · Erase Suspend / Resume modes: Read and program another Sector during Erase Suspend Mode · 0. 23 µm triple-metal double-poly triple-well CMOS Flash Technology · Low Vcc write inhibit < 3. 2V · 100K endurance cycle · Package Options - 32-pin PDIP - 32-pin PLCC - 32-pin TSOP (Type 1) · Commercial and Industrial Temperature Ranges · - · Low Standby Current - 1µA CMOS standby current-typical - 1mA TTL standby current · Low Power Active Current - 30mA active read current - 30mA program/erase current GENERAL DESCRIPTION The EN29F040A is a 4-Megabit, electrically erasable, read/write non-volatile flash memory. Organized into 512K words with 8 bits per word, the 4M of memory is arranged in eight uniform sectors of 64Kbytes each. Any byte can be programmed typically in 10µs. The EN29F040A features 5. 0V voltage read and write operation, with access times as fast as 45ns to eliminate the need for WAIT states in high-performance microprocessor systems. [. . . ] For Chip Erase, the DATA polling is valid after the rising edge of the sixth W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last rising edge of the sector erase W E or C E pulse. DATA Polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address used is in a protected sector. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing diagram is shown in Figure 8. DQ6 Toggle Bit I The EN29F040A provides a "Toggle Bit" on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by toggling OE or CE ) will result in DQ6 toggling between "zero" and "one". Once the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the last rising edge of the Sector Erase W E pulse. The Toggle Bit is also active during the sector erase time-out window. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. B, Issue Date: 2004/04/01 EN29F040A In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all selected sectors are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read mode without changing data in all protected sectors. Toggling either CE or OE will cause DQ6 to toggle. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9. DQ5 Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1. " (The Toggle Bit (DQ6) should also be checked at this time to make sure that the DQ5 is not a "1" due to the device having returned to read mode. ) This is a failure condition that indicates the program or erase cycle was not successfully completed. [. . . ] AC Waveforms for Chip/Sector Erase Operations Notes: 1. SA is the Sector address for Sector erase. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 27 ©2003 Eon Silicon Solution, Inc. , www. essi. com. tw Rev. B, Issue Date: 2004/04/01 EN29F040A SWITCHING WAVEFORMS (continued) Figure 7. PA is address of the memory location to be programmed. [. . . ]