User manual MATLAB SIMULINK HDL CODER 1
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Manual abstract: user guide MATLAB SIMULINK HDL CODER 1
Detailed instructions for use are in the User's Guide.
[. . . ] Simulink® HDL CoderTM 1 User's Guide
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For contact information about worldwide offices, see the MathWorks Web site. Simulink® HDL CoderTM User's Guide © COPYRIGHT 20062010 by The MathWorks, Inc.
The software described in this document is furnished under a license agreement. The software may be used or copied only under the terms of the license agreement. [. . . ] The following figures illustrate continuous data streaming. Each data frame corresponds to a stream of N input data values, where N is the FFT length.
Continuous Data Streaming with Start Signal Held High
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The hdldemolib Block Library
Note The start signal can be a single cycle pulse; it need not be held high for the entire data frame. When processing for a frame begins, further pulses on start do not affect processing of that frame. However, a start pulse must occur at the beginning of each data frame.
Continuous Data Streaming With Pulsed Start Signal
Non-Continuous Data Streaming Timing
In this mode, the HDL Streaming FFT block receives continuous bursts of streaming data at din. After an initial delay, the block produces non-continuous bursts of streaming data at dout. Breaks occur between data frames when the following condition exist: · The start signal does not assert every N clock cycles (where N is the FFT length) · The start signal is not continuously held high. Non-continuous data streaming mode allows you more flexibility in determining the intervals between input data streams.
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HDL Streaming FFT
Initial Delay
The initial delay of the HDL Streaming FFT block is the interval between the following times: · The time the block begins to receive the first frame of input data · The time the block asserts dvalid and produces the first valid output data. The initial delay represents the time the block uses to load a data frame, calculate the FFT, and output the beginning of the first output frame. The following figure illustrates the initial delay.
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The hdldemolib Block Library
If you select the block option Display computed intitial delay on mask, the block icon displays the intial delay. The display represents the delay time as Z-n, where n is the delay time in samples.
HDL Implementation and Implementation Parameters
Implementation: default Implementation Parameters: InputPipeline, OutputPipeline
Parameters and Dialog Box
The following figure shows the HDL Streaming FFT block dialog box, with all parameters at their default settings.
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HDL Streaming FFT
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The hdldemolib Block Library
FFT Length Default: 1024 The FFT length must be a power of 2, in the range 23 to 216. Rounding mode Default: Floor The HDL Streaming FFT block supports all rounding modes of the Signal Processing Blockset FFT block. See also the FFT block reference section in the Signal Processing Blockset documentation. Overflow mode Default: Wrap The HDL Streaming FFT block supports all overflow modes of the Signal Processing Blockset FFT block. See also the FFT block reference section in the Signal Processing Blockset documentation. Sine table Default: Same word length as input Choose how you specify the word length of the values of the sine table. The fraction length of the sine table values is always equal to the word length minus one. · When you select Same word length as input, the word lengths of the sine table values match the word lengths of the block inputs. · When you select Specify word length, you can enter the word length of the sine table values, in bits, in the Sine table word length field. The sine table values do not obey the Rounding mode and Overflow mode parameters. They always saturate and always round to Nearest. Product output
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HDL Streaming FFT
Default: Same as input Use this parameter to specify how you want to designate the product output word and fraction lengths: · When you select Same as input, these characteristics match the characteristics of the input to the block. · Binary point scaling: Enter the word length and the fraction length of the product output, in bits, in the Product word length and Product fraction length fields. [. . . ] The next section, "Defaults for Test Bench Code Generation" on page 18-30, summarizes the defaults that are specific to generated test bench code. For detailed descriptions of each property and its effect on generated code, see Chapter 16, "Properties -- Alphabetical List", and Chapter 17, "Property Reference".
Generating Stimulus and Output Data
makehdltb generates test data from signals connected to inputs of the subsystem under test. Sample values for each stimulus signal are computed and stored for each time step of the simulation. The signal data is represented as arrays in the generated test bench code.
To help you validate generated HDL code, makehdltb also generates output data from signals connected to outputs of the subsystem under test. [. . . ]
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