User manual MAXTOR CFA810A

[. . . ] CFA810A/CFA1080A Intelligent Disk Drive Product Manual Production Release Per EC 5687 P/N 00550-001 Revision A May 1994 3081 Zanker Road San Jose, CA 95134-2128 (408) 456-4500 FCC Notice This equipment generates and uses radio frequency energy and, if not installed and used properly; that is, in strict accordance with the manufacturer's instructions, may cause interference to radio and television reception. It has been designed to provide reasonable protection against such interference in a residential installation. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause interference to radio or television reception, which can be determined by turning the equipment on and off, you are encouraged to try to correct the interference by one or more of the following measures: · · · Reorient the receiving antenna. [. . . ] Immediately following transfer of 256 words of data after host write of the command register with a Write, Format Track, or Write Buffer command. Immediately following transfer of 256 words of data and the ECC bytes after a host write of the Command register with a Write Long command. - - When BSY is active, any host read of a Task File register is inhibited and the Status register is read instead. · DRDY is the drive ready indication. When there is an error, this bit is not changed until the Status register is read by the host, at which time the bit again indicates the current readiness of the drive. This bit will be reset at power-up and remain reset until the drive is up to speed and ready to accept a command. Technical Reference Manual Page 45 Chapter 6 Register Addresses and Functions · DWF is the drive write fault bit. When there is an error, this bit is not changed until the Status register is read by the host, at which time the bit again indicates the current write fault status. It is an indication that the actuator is on track. When there is an error, this bit is not changed until the Status register is read by the host, at which time the bit again indicates the current readiness of the drive. This bit will be reset at power-up and will remain reset until the drive is up to speed and ready to accept a command. DRQ is the data request bit, which indicates that the drive is ready for transfer of a word or a byte of data between the host and the Data register. CORR is the corrected data bit, which is set: - - when a correctable data error has been encountered and the data has been corrected on a read verify if any sector was corrected the bit is valid · · · This condition will not terminate either a Multi-Sector Read or a Read Multiple command. · · IDX is the index bit which is set once per disk revolution. ERR is the error bit, which indicates that the previous command ended in some type of error. The other bits in the Status register, as well as the bits in the Error register, will have additional information as to the cause of the error. Alternate Status Register Port Address: Chip Select: Register Address: Function: 3F6 -HOST CS1 6 Read only Description: This register contains the same information as the Status register in the Task File. The only difference is that reading this register does not imply interrupt acknowledge to reset a pending interrupt. The bits in this register are defined below: Bit 7 BSY Bit 6 DRDY Bit 5 DWF Bit 4 DSC Bit 3 DRQ Bit 2 CORR Bit 1 IDX Bit 0 ERR See the description of the Status register for definitions of the bits in this register. Page 46 Filepro CFA810A/CFA1080A Register Addresses and Functions Chapter 6 Digital Output Register Port Address: Chip Select: Register Address: Function: 3F6 -HOST CS1 6 Write only Description: This register contains two control bits as follows: Bit 7 not used where: · Bit 6 not used Bit 5 not used Bit 4 not used Bit 3 not used Bit 2 SRST Bit 1 -IEN Bit 0 not used SRST is the host software reset bit. The drive is held reset when this bit is active, and enabled when this bit is inactive. -IEN is the enable bit for this disk drive interrupt to the host. - - When this bit is active (=0) and the drive is selected, the host interrupt, +IRQ, is enabled through a tri-state buffer to the host. When this bit is inactive (=1), or the drive is not selected, the +IRQ pin will be in a high impedance state, regardless of the presence or absence of a pending interrupt. · Technical Reference Manual Page 47 Chapter 6 Register Addresses and Functions Drive Address Register Port Address: Chip Select: Register Address: Function: 3F7 -HOST CS1 7 Read only Description: This register loops back the drive select and head select addresses of the currently selected drive. The bits in this register are as follows: Bit 7 RSVD where: · Bit 6 -WTG Bit 5 -HS3 Bit 4 -HS2 Bit 3 -HS1 Bit 2 -HS0 Bit 1 -DS1 Bit 0 -DS0 RSVD is reserved and negated by the drive. When the host reads the drive address register, this bit must be in a high impedance state. [. . . ] The host may then read the Task File to determine what error has occurred, and on which sector. Technical Reference Manual Page 75 Chapter 7 Command Set A Write Long may be executed by setting the long bit in the command code. The Write Long command writes the data and the ECC bytes directly from the sector buffer; the drive will not generate the ECC bytes itself for the Write Long command. Data byte transfers are 16-bit transfers and ECC bytes are 8bit transfers. Write Caching Write caching is activated by setting the Feature Word bit 2. Once write caching is active, the Write Sector(s) command is cached. [. . . ]