User manual MAXTOR PARALLEL SCSI INTERFACE

[. . . ] Parallel SCSI Interface Ultra 160 Ultra 320 Parallel SCSI Interface Ultra 160 Ultra 320 ©2006, Seagate Technology LLC All rights reserved Publication number: 100293069, Rev. A March 2006 Seagate and Seagate Technology are registered trademarks of Seagate Technology LLC. SeaTools, SeaFONE, SeaBOARD, SeaTDD, and the Wave logo are either registered trademarks or trademarks of Seagate Technology LLC. Other product names are registered trademarks or trademarks of their owners. [. . . ] The minimum data invalid time is four transfer periods. This ensures a maximum run length of three cycles for P1. The data invalid state shall last an even number of transfer periods. From the data invalid state, the sending SCSI device port may resume sending data by reversing the phase of P1 again. P1 has the same transmit setup and hold time requirements as data and shall always be detected by the receiving device on the assertion edge of the delayed clocked REQ or ACK signal. See Figure 10 for examples of how the P1 signal is used to determine when the REQ or ACK transition clocks valid data. DT Data In phase example P1 REQ X X X X X X OOOOOOOOOO X X X X X X X X X X X X OOOOOO X X X X OOOOOO DT Data Out phase example P1 ACK X X X X X X OOOOOOOOOO X X X X OOX X X X X X OOOOOO X X X X OOOOOO O - Data is valid on indicated transition X - Data is invalid on indicated transition Figure 10. Use of P1 to establish data valid and data invalid states 3. 5. 3. 2. 1 Starting pacing transfers at end of training pattern See Section 3. 5. 3. 1 for the description of starting a data valid state after a training pattern. 3. 5. 3. 2. 2 Starting pacing transfers with no training pattern Before starting the DT DATA IN phase, the SCSI target port shall wait at least two system deskew delays after the SEL signal is negated before the first assertion of the REQ signal. The DT DATA IN phase without training starts on the first assertion of REQ if the SEL is not asserted. The SCSI target port shall begin pacing transfers only after meeting all the following: · signal restrictions between information transfer phases listed in Section 3. 10; · the signal restrictions between a RESELECTION phase and a DT DATA IN phase listed in Section 3. 3. 2; or · the signal restrictions between a SELECTION phase and a DT DATA OUT phase listed in Section 3. 2. 1. 2. The SCSI target port shall begin pacing transfers by: · simultaneously with the assertion of REQ, the SCSI target port shall begin asserting and negating P1 at twice the negotiated transfer period (e. g. , 12. 5 ns for Fast-160); · SCSI target port shall assert and negate P1 at least 8 times [e. g. , (2 x 6. 25 ns) x 8 = 100 ns at Fast-160]; and · the SCSI target port may establish a data valid state as described in Section 3. 5. 3. 2. The DT DATA OUT phase without training starts on the first assertion of REQ if the SEL is not asserted. 72 Parallel SCSI Interface Product Manual, Rev. A The SCSI target port shall begin pacing transfers only after meeting all the following: · signal restrictions between information transfer phases listed in Section 3. 10; · the signal restrictions between a RESELECTION phase and a DT DATA IN phase listed in Section 3. 3. 2; or · the signal restrictions between a SELECTION phase and a DT DATA OUT phase listed in Section 3. 2. 1. 2. The SCSI initiator port shall begin pacing transfers by: · simultaneously with the assertion of ACK the SCSI initiator port shall begin asserting and negating P1 at twice the negotiated transfer period (e. g. , 12. 5 ns for Fast-160); · SCSI initiator port shall assert and negate P1 at least 8 times (e. g. , (2 x 6. 25 ns) x 8 = =100 ns at Fast-160); and · the SCSI initiator port may establish a data valid state as described in Section 3. 5. 3. 2. 3. 5. 3. 2. 3 Ending pacing transfers After transmitting the last data word of a DT DATA IN phase, the SCSI target port shall end pacing by waiting for all REQs to be responded to by ACKs then negate the REQ and P1 signals. After the SCSI target port stops asserting and negating REQ, it shall not assert REQ again until the requirements in Section 3. 10 are met. After transmitting the last data word of a DT DATA OUT phase, the SCSI initiator port shall: · continue asserting and negating the ACK and P1 signals until it detects a change to the C/D, I/O, or MSG signals; and · negate the ACK and P1 signals within 200 ns of detecting a change to the C/D, I/O, or MSG signals. When the SCSI target port changes from a DT DATA OUT phase to any other phase it shall wait at least a bus settle delay plus a data release delay before asserting REQ and shall ignore any ACK transitions for at least a bus settle delay plus a data release delay after transitioning the C/D, I/O, or MSG signals. 3. 5. 3. 3 Paced information unit transfer Information units shall be transferred on the DT DATA OUT phase and the DT DATA IN phase, and the information units' embedded iuCRC shall be used to detect information unit data errors. If the I/O signal is true (i. e. , transfer to the SCSI initiator port) and the phase of the P1 signal indicates data is valid, to transfer SPI information units the SCSI target port: (a) shall drive the DB(15-0) signals to their values simultaneous with the next REQ signal assertion; (b) shall hold the DB(15-0) signals valid for a minimum of one transmit hold time; (c) shall drive the DB(15-0) signals to their values simultaneous with the next REQ signal negation; and (d) shall hold the DB(15-0) signals valid for a minimum of one transmit hold time. If the I/O signal is true (i. e. , transfer to the SCSI initiator port), to receive SPI information units the SCSI initiator port shall: (a) read the value on the DB(15-0) signals within one receive hold time of the transition of the REQ signal; and (b) respond with an ACK signal assertion after each REQ assertion/negation pair. If the I/O signal is false (i. e. , transfer to the SCSI target port) and the phase of the P1 signal indicates data is valid, to transfer SPI information units the SCSI initiator port: (a) shall wait until detecting a REQ assertion; (b) shall drive the DB(15-0) signals to their values simultaneous with the next ACk signal assertion; (c) shall hold the DB(15-0) signals valid for a minimum of one transmit hold time; (d) shall drive the DB(15-0) signals to their values simultaneous with the next ACK signal negation; Parallel SCSI Interface Product Manual, Rev. A 73 and (e) shall hold the DB(15-0) signals valid for a minimum of one transmit hold time. [. . . ] see Command Descriptor Block Change Definition command 149 changed operating definition 150 characteristic logical 51 check condition 131, 137, 138, 142, 145 check condition status 5, 6, 142, 143, 144, 146, 149, 150 chip noise in receiver 27 clear ACA message 106 clear ACA task management function 143 clear queue 146 clear task set 138 clear task set message 106 client 4, 9 client-server 4 model 4 clock jitter 27 code description 157 Parallel SCSI Interface Product Manual, Rev. A 161 code value reserved 131 command 4, 6 aborted 4 completed 5 ended 6 linked 7 overlapped 143 SCSI-3 standards 2 single, example 140 third party 11 unlinked 11 untagged 149 command complete message 140, 141 command completion 131 command data 5 command data signal 29 Command Descriptor Block SPI command information unit 119, 120 command descriptor block 5, 131, 135, 144, 150 10-byte commands 133 12-byte commands 134 16-byte commands 134 6-byte commands 133 control field 136 format 133 linked 7 typical variable length 135 command descriptor byte control byte 11 command phase 75 command processing 142 command queue 138 command set 149 command structure packetized 131 common access method SCSI-3 standards 2 completed command 5 completed task 5 compliance with a standard 7 condition met 138 confirmation 5 confirmed protocol service 5 confirmed service reply 6 connectors 12 contingent allegiance 5 NACA=0 145 contingent allegiance condition 6, 143 control byte 142, 143 control field 136 control mode page 5, 143, 148 control/data SCSI bus signal 15 covered signal 155 CRC 82 CRC protection 1 CRC. see cyclic redundancy check CRC-32 82 current task 5, 8 cyclic redundancy check 5, 7, 82 cylinder boundary 141 D Data SPI data information unit 125 SPI data stream information unit 126 data 6 data bus 29 data field 5 data group 5, 8 data group transfer 5 data group transfers 1, 38 data in phase 131, 136 Data Length SPI L_Q information unit 122, 123 data length field 7 data out phase 131, 136 data transfer modes 37 DB(15--0) 17 DB(7--0) 17 DB(P_CRCA) signals 33 DB(P1) signals 33 default self-test 151 deferred error 149 delay 27 de-skewed data valid window 28 deskewing 74 destination device 5 device destination 5 SCSI 9 source 10 device server 3, 5 device service request 5 response 5 device service request 6 differential 5 differential drivers and receivers 5 differential sense SCSI bus signal 15 DIFFSENS. see Differential Sense disc media 140 disconnect 5 capability 140 example 141 disconnect message 87, 141 Disconnect Privilege Identify message format 87 162 Parallel SCSI Interface Product Manual, Rev. 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